BibSLEIGH — Proceedings of the Ninth Conference on Design, Automation and Test in Europe

Proceedings of the Ninth Conference on Design, Automation and Test in Europe
DATE, 2005.

SYS

@proceedings{DATE-2005,
	address       = "Munich, Germany",
	isbn          = "0-7695-2288-2",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Ninth Conference on Design, Automation and Test in Europe}",
	year          = 2005,
}

Contents (312 items)

DATE-2005-KirsteinSSHVH04 #monitoring: A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring (KUK, JS, TS, CH, TV, AH), pp. 210–214.
DATE-2005-SturmLSGZ04: Optical Receiver IC for CD/DVD/Blue-Laser Application (JS, ML, HS, SG, HZ), pp. 215–218.
DATE-2005-AndersenBTBBHM04 #pipes and filters: A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS (TNA, AB, FT, JB, TEB, BH, ØM), pp. 219–222.
DATE-2005-SandnerCSHK04 #power management: A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS (CS, MC, AS, TH, FK), pp. 223–226.
DATE-2005-BernardiMQR04 #approach #logic #testing #using: Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study (PB, GM, FQ, MSR), pp. 228–233.
DATE-2005-MelloMCM04 #multi #named #network: MultiNoC: A Multiprocessing System Enabled by a Network on Chip (AM, LM, NC, FGM), pp. 234–239.
DATE-2005-Hillman04 #power management #reduction #using: Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm (DH), pp. 240–246.
DATE-2005-GalanisMTSG04 #clustering #configuration management #hybrid #platform: A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms (MDG, AM, GT, DS, CEG), pp. 247–252.
DATE-2005-RissaDL04 #configuration management #embedded #evaluation #modelling: Evaluation of SystemC Modelling of Reconfigurable Embedded Systems (TR, AD, WL), pp. 253–258.
DATE-2005-UllmannJB04 #configuration management #hardware: Hardware Support for QoS-based Function Allocation in Reconfigurable Systems (MU, WJ, JB), pp. 259–264.
DATE-2005-BorgattiCRLMFP04 #configuration management #design #multi #verification: An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems (MB, AC, UR, JLL, IM, FF, GP), pp. 266–271.
DATE-2005-FalconeriNR04 #modelling #reuse #verification: Common Reusable Verification Environment for BCA and RTL Models (GF, WN, NR), pp. 272–277.
DATE-2005-MacBethHG04a #assembly #verification: An Assembler Driven Verification Methodology (ADVM) (JSM, DH, KG), pp. 278–283.
DATE-2005-UmezawaS04 #verification: A Formal Verification Methodology for Checking Data Integrity (YU, TS), pp. 284–289.
DATE-2005-HabibiAMT04 #design #interface #on the #verification: On the Design and Verification Methodology of the Look-Aside Interface (AH, AIA, OAM, ST), pp. 290–295.
DATE-2005-Kong #challenge: SoC in Nanoera: Challenges and Endless Possibility (JTK), p. 2.
DATE-2005-LopezCLS #estimation #quality: A High Quality/Low Computational Cost Technique for Block Matching Motion Estimation (SL, GMC, JFL, RS), pp. 2–7.
DATE-2005-Hughes #challenge: Striking a New Balance in the Nanometer Era: First-Time-Right and Time-to-Market Demands Versus Technology Challenges (GH), p. 3.
DATE-2005-BaradaranD #algorithm #architecture #configuration management: A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures (NB, PCD), pp. 6–11.
DATE-2005-FahmyCL #detection #hardware #markov: Hardware Acceleration of Hidden Markov Model Decoding for Person Detection (SAF, PYKC, WL), pp. 8–13.
DATE-2005-KimKPJC #architecture #configuration management #optimisation #pipes and filters #resource management: Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization (YK, MK, CP, JJ, KC), pp. 12–17.
DATE-2005-EeckhautDSCS #scalability #video: A Hardware-Friendly Wavelet Entropy Codec for Scalable Video (HE, HD, BS, MC, DS), pp. 14–19.
DATE-2005-LyseckyV #case study #clustering #hardware #using: A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning (RLL, FV), pp. 18–23.
DATE-2005-BurchardHC #memory management #realtime #streaming: A Real-Time Streaming Memory Controller (AB, EHN, AC), pp. 20–25.
DATE-2005-CheungLC #configuration management: Reconfigurable Elliptic Curve Cryptosystems on a Chip (RCCC, WL, PYKC), pp. 24–29.
DATE-2005-StecheleCHS #information management #visual notation: A Coprocessor for Accelerating Visual Information Processing (WS, LAC, SH, JLS), pp. 26–31.
DATE-2005-RodriguesC #compilation #design #framework: An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs (RR, JMPC), pp. 30–31.
DATE-2005-HuotDFR #architecture #logic #multi: FPGA Architecture for Multi-Style Asynchronous Logic (NH, HD, LF, MR), pp. 32–33.
DATE-2005-SilvaB #architecture #design #pipes and filters #throughput #trade-off: Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures (SVS, SB), pp. 32–37.
DATE-2005-GielenDCDJMV #design #question: Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? (GGEG, WD, PC, DD, EJ, KM, TV), pp. 36–42.
DATE-2005-ElbazTSGABBR #encryption #hardware #overview: Hardware Engines for Bus Encryption: A Survey of Existing Techniques (RE, LT, GS, PG, CA, MB, CB, JBR), pp. 40–45.
DATE-2005-GoelM #design #framework #multi #testing: On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips (SKG, EJM), pp. 44–49.
DATE-2005-ThullS #embedded #implementation #performance: Performance Considerations for an Embedded Implementation of OMA DRM 2 (DT, RS), pp. 46–51.
DATE-2005-SehgalLOC #testing: Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores (AS, FL, SO, KC), pp. 50–55.
DATE-2005-CilardoMMR #architecture #encryption #novel: A Novel Unified Architecture for Public-Key Cryptography (AC, AM, NM, LR), pp. 52–57.
DATE-2005-BeckBKPLP #design #generative #implementation #logic #quality: Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality (MB, OB, MK, FP, XL, RP), pp. 56–61.
DATE-2005-TiriV05a #design: A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs (KT, IV), pp. 58–63.
DATE-2005-AmoryLMM #architecture #multi #reduction #reuse: Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture (AMA, ML, FGM, EIM), pp. 62–63.
DATE-2005-YangWVSX #approach #design: Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach (SY, WW, NV, DNS, YX), pp. 64–69.
DATE-2005-Edwards #challenge #hardware #synthesis: The Challenges of Hardware Synthesis from C-Like Languages (SAE), pp. 66–67.
DATE-2005-Dean #concurrent #integration #realtime #synthesis #thread: Software Thread Integration and Synthesis for Real-Time Applications (AGD), pp. 68–69.
DATE-2005-DykaL #encryption #hardware #implementation #performance: Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba’s Method (ZD, PL), pp. 70–75.
DATE-2005-Oliver #design #uml: Applying UML and MDA to Real Systems Design (IO), pp. 70–71.
DATE-2005-Marculescu #bound #design #energy #fault tolerance: Energy Bounds for Fault-Tolerant Nanoscale Designs (DM), pp. 74–79.
DATE-2005-FaroukS #algorithm #communication #encryption #hybrid #implementation #security: An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security (HAF, MS), pp. 76–81.
DATE-2005-KaulSBMA #design #fault: DVS for On-Chip Bus Designs Based on Timing Error Correction (HK, DS, DB, TNM, TMA), pp. 80–85.
DATE-2005-PradeepVBK #agile #on-demand: FPGA based Agile Algorithm-On-Demand Co-Processor (RP, SV, SB, VK), pp. 82–83.
DATE-2005-CaiL #memory management #power management: Joint Power Management of Memory and Disk (LC, YHL), pp. 86–91.
DATE-2005-Wolf #multi: Multimedia Applications of Multiprocessor Systems-on-Chips (WW), pp. 86–89.
DATE-2005-Holt #past present future: Wireless LAN: Past, Present, and Future (KH), pp. 92–93.
DATE-2005-YuWCHYB #architecture #design #network: Assertion-Based Design Exploration of DVS in Network Processor Architectures (JY, WW, XC, HH, JY, FB), pp. 92–97.
DATE-2005-BlazquezLWGPC #architecture: Direct Conversion Pulsed UWB Transceiver Architecture (RB, FSL, DDW, BPG, JP, AC), pp. 94–95.
DATE-2005-Simunic #power management: Power Saving Techniques for Wireless LANs (TS), pp. 96–97.
DATE-2005-KienleBW: A Synthesizable IP Core for DVB-S2 LDPC Code Decoding (FK, TB, NW), pp. 100–105.
DATE-2005-PanainteBV #hardware #scheduling: Instruction Scheduling for Dynamic Hardware Configurations (EMP, KB, SV), pp. 100–105.
DATE-2005-DullerTPGR: picoArray Technology: The Tool’s Story (AD, DT, GP, AG, WR), pp. 106–111.
DATE-2005-ResanoMC #configuration management #hardware #heuristic #hybrid #runtime #scheduling: A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware (JR, DM, FC), pp. 106–111.
DATE-2005-GuoBNV #c #generative: Optimized Generation of Data-Path from C Codes for FPGAs (ZG, BB, WAN, KAV), pp. 112–117.
DATE-2005-PapaefstathiouOKKMN #network #queue: Queue Management in Network Processors (IP, TO, GK, CK, IM, AN), pp. 112–117.
DATE-2005-ContiM #analysis #standard: System Level Analysis of the Bluetooth Standard (MC, DM), pp. 118–123.
DATE-2005-MartensG #integration #orthogonal #polynomial #simulation #using: Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series (EM, GGEG), pp. 120–125.
DATE-2005-TakachBB #c #design #hardware: C Based Hardware Design for Wireless Applications (AT, BB, TB), pp. 124–129.
DATE-2005-LiuFYO #analysis #correlation #graph #modelling: Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing (FL, JJF, DVY, SO), pp. 126–131.
DATE-2005-RaabeBAZ #architecture #detection #hardware #simulation: Hardware Accelerated Collision Detection — An Architecture and Simulation Results (AR, BB, JKA, GZ), pp. 130–135.
DATE-2005-MangassarianA #analysis #on the #statistics: On Statistical Timing Analysis with Inter- and Intra-Die Variations (HM, MA), pp. 132–137.
DATE-2005-HeusalaL #configuration management #modelling #product line: Modeling of a Reconfigurable OFDM IP Block Family For an RF System Simulator (HH, JL), pp. 136–137.
DATE-2005-BadaouiV #multi #performance #synthesis: Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis (RFB, RV), pp. 138–143.
DATE-2005-KimKKSCCKE #architecture #modelling #performance #transaction: Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture (YTK, TK, YK, CS, EYC, KMC, JTK, SKE), pp. 138–139.
DATE-2005-Lyons #design #embedded: Meeting the Embedded Design Needs of Automotive Applications (WL), pp. 142–147.
DATE-2005-NoguchiN #monitoring #multi: On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits (KN, MN), pp. 146–151.
DATE-2005-MayerSM #debugging #multi: Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs (AM, HS, KDMM), pp. 148–152.
DATE-2005-KeezerGMT #low cost #multi #using: Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL (DCK, CG, AMM, NT), pp. 152–157.
DATE-2005-JeffreyCPLRR #configuration management #integration #monitoring #online #safety #using: The Integration of On-Line Monitoring and Reconfiguration Functions using IEEE1149.4 Into a Safety Critical Automotive Electronic Control Unit (CJ, RC, SP, ML, AR, SR), pp. 153–158.
DATE-2005-NegreirosCS #evaluation #low cost #using: Noise Figure Evaluation Using Low Cost BIST (MN, LC, AAS), pp. 158–163.
DATE-2005-Horsky #safety: LC Oscillator Driver for Safety Critical Applications (PH), pp. 159–164.
DATE-2005-BiswasLBP #specification: Specification Test Compaction for Analog Circuits and MEMS (SB, PL, RD(B, LTP), pp. 164–169.
DATE-2005-StaschulatESW #analysis #performance: Context Sensitive Performance Analysis of Automotive Applications (JS, RE, AS, FW), pp. 165–170.
DATE-2005-KherijiDCM #approach #optimisation #testing: Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach (RK, VD, JLC, SM), pp. 170–171.
DATE-2005-ZiegenbeinBFBRS #development #modelling #named: AutoMoDe — Model-Based Development of Automotive Software (DZ, PB, UF, AB, JR, BS), pp. 171–177.
DATE-2005-SyriHM #metric: EEE 1149.4 Compatible ABMs for Basic RF Measurements (PS, JH, MM), pp. 172–173.
DATE-2005-SavioliCCF #approach #fault: Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits (CES, CCC, JVC, ACdMF), pp. 174–175.
DATE-2005-Conti #analysis #architecture #power management: SystemC Analysis of a New Dynamic Power Management Architectur (MC), pp. 177–178.
DATE-2005-AroraRRJ #embedded #monitoring #runtime: Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring (DA, SR, AR, NKJ), pp. 178–183.
DATE-2005-ChappellMPOFS #adaptation #generative #realtime #safety: Exploiting Real-Time FPGA Based Adaptive Systems Technology for Real-Time Sensor Fusion in Next Generation Automotive Safety Systems (SC, AM, DP, DO, BF, CS), pp. 180–185.
DATE-2005-KaoM #energy: Energy-Aware Routing for E-Textile Applications (JCK, RM), pp. 184–189.
DATE-2005-FanucciGIMR #design #framework #platform: Platform Based Design for Automotive Sensor Conditioning (LF, AG, FI, CM, AR), pp. 186–191.
DATE-2005-GhoshG #distributed #locality #named #network #protocol #scheduling: LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks (AG, TG), pp. 190–195.
DATE-2005-AmatoCMP #precise: Realization of a Virtual Lambda Sensor on a Fixed Precision System (PA, NC, MDM, FP), pp. 192–197.
DATE-2005-BougardCDCD #energy #modelling #network #performance #standard: Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives (BB, FC, DCD, AC, WD), pp. 196–201.
DATE-2005-StagniGLBR #design #detection: Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection (CS, CG, ML, LB, BR), pp. 198–203.
DATE-2005-RaiM #modelling #network: Lifetime Modeling of a Sensor Network (VR, RNM), pp. 202–203.
DATE-2005-MilevB #analysis: A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems (MM, RB), pp. 204–208.
DATE-2005-RosselloCBKS #concurrent #performance: A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs (JLR, VC, SAB, AK, JS), pp. 206–211.
DATE-2005-HassanADE #power management #process #reduction: Activity Packing in FPGAs for Leakage Power Reduction (HH, MA, AED, MIE), pp. 212–217.
DATE-2005-SrinivasanLV #architecture #clustering: Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures (SS, LL, NV), pp. 218–223.
DATE-2005-MukhopadhyayBR #analysis #logic #modelling: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits (SM, SB, KR), pp. 224–229.
DATE-2005-TsaiVXI #network: Leakage-Aware Interconnect for On-Chip Network (YFT, NV, YX, MJI), pp. 230–231.
DATE-2005-NolletMAM #configuration management #hardware #resource management #runtime: Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles (VN, TM, PA, JYM), pp. 234–239.
DATE-2005-HungBK #multi #programmable #symmetry: Symmetric Multiprocessing on Programmable Chips Made Easy (AH, WDB, AAK), pp. 240–245.
DATE-2005-GenkoAMMHC #framework: A Complete Network-On-Chip Emulation Framework (NG, DA, GDM, JMM, RH, FC), pp. 246–251.
DATE-2005-NolletAMV #low cost #migration: Low Cost Task Migration Initiation in a Heterogeneous MP-SoC (VN, PA, JYM, DV), pp. 252–253.
DATE-2005-StuijkBMG #data type #multi #predict #scalability: Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip (SS, TB, BM, MG), pp. 254–255.
DATE-2005-MullerTAL #design #multi #power management #top-down: Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit (PM, AT, SMA, YL), pp. 258–263.
DATE-2005-TangWD #complexity #power management #synthesis: MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption (HT, YW, AD), pp. 264–269.
DATE-2005-SoensPWD #analysis #simulation: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (CS, GVdP, PW, SD), pp. 270–275.
DATE-2005-BarrandonCH #design #pipes and filters: Systematic Figure of Merit Computation for the Design of Pipeline ADC (LB, SC, DH), pp. 277–278.
DATE-2005-ChienCLMRM #optimisation #pipes and filters: Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters (YTC, DC, JHL, GKM, RAR, TM), pp. 279–280.
DATE-2005-KrishnaswamyVMH #evaluation #matrix #probability #reliability: Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices (SK, GFV, ILM, JPH), pp. 282–287.
DATE-2005-DhillonDC #analysis #optimisation: Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits (YSD, AUD, AC), pp. 288–293.
DATE-2005-NeiroukhS #statistics #using: Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques (ON, XS), pp. 294–299.
DATE-2005-CarterOS #concurrent #fault #modelling #testing: Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown (JRC, SO, DJS), pp. 300–305.
DATE-2005-AsadiT #estimation #probability: An Accurate SER Estimation Method Based on Propagation Probability (GA, MBT), pp. 306–307.
DATE-2005-Lopez-OngilGPE #fault #performance: Techniques for Fast Transient Fault Grading Based on Autonomous Emulation (CLO, MGV, MPG, LEA), pp. 308–309.
DATE-2005-HamannE #optimisation #search-based: TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques (AH, RE), pp. 312–317.
DATE-2005-WongLLHP #realtime #scheduling: Scheduling of Soft Real-Time Systems for Context-Aware Applications (JLW, WL, FL, LH, MP), pp. 318–323.
DATE-2005-RinconMBL #design pattern #hardware #reuse: Model Reuse through Hardware Design Patterns (FR, FM, JB, JCL), pp. 324–329.
DATE-2005-Abdel-HamidTA #design: A Public-Key Watermarking Technique for IP Designs (ATAH, ST, EMA), pp. 330–335.
DATE-2005-Martin #component #design #transaction: Design of a Virtual Component Neutral Network-on-Chip Transaction Layer (PM), pp. 336–337.
DATE-2005-YardiHMH #multi #power management #quality: Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing (SMY, MSH, TLM, DSH), pp. 340–345.
DATE-2005-IranliFP #named #scalability: HEBS: Histogram Equalization for Backlight Scaling (AI, HF, MP), pp. 346–351.
DATE-2005-OgrasM #approach #architecture #communication #composition #energy #synthesis #using: Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach (ÜYO, RM), pp. 352–357.
DATE-2005-IshiharaF #power management: A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors (TI, FF), pp. 358–363.
DATE-2005-MiramondD #architecture #configuration management #design: Design Space Exploration for Dynamically Reconfigurable Architectures (BM, JMD), pp. 366–371.
DATE-2005-JhumkaKH #approach #design #embedded: A Dependability-Driven System-Level Design Approach for Embedded Systems (AJ, SK, SAH), pp. 372–377.
DATE-2005-LavagnoPSW #design #slicing: A Time Slice Based Scheduler Model for System Level Design (LL, CP, VS, YW), pp. 378–383.
DATE-2005-LeeCALK #hardware #predict #transaction: A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation (JGL, MKC, KYA, SHL, CMK), pp. 384–389.
DATE-2005-GadkariR #automation #monitoring #specification #synthesis #using #visual notation: Automated Synthesis of Assertion Monitors using Visual Specifications (AAG, SR), pp. 390–395.
DATE-2005-StittV #approach #clustering #decompiler #platform: A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms (GS, FV), pp. 396–397.
DATE-2005-AgarwalCB #optimisation #statistics #using: Statistical Timing Based Optimization using Gate Sizing (AA, KC, DB), pp. 400–405.
DATE-2005-TeslenkoD #algorithm #graph #performance: An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs (MT, ED), pp. 406–411.
DATE-2005-MishchenkoB #network #optimisation #satisfiability: SAT-Based Complete Don’t-Care Computation for Network Optimization (AM, RKB), pp. 412–417.
DATE-2005-MishchenkoBJVY #equation #performance #using: Efficient Solution of Language Equations Using Partitioned Representations (AM, RKB, JHRJ, TV, NY), pp. 418–423.
DATE-2005-BouesseRDG #formal method: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement (GFB, MR, SD, FG), pp. 424–429.
DATE-2005-MartinelliD #bound #composition #set: Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition (AM, ED), pp. 430–431.
DATE-2005-MarkovM #encryption #hardware #logic: Uniformly-Switching Logic for Cryptographic Hardware (ILM, DM), pp. 432–433.
DATE-2005-YangHSP #logic #multi #quantum #synthesis #using: Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory (GY, WNNH, XS, MAP), pp. 434–435.
DATE-2005-MajhiAGLEB #evaluation #industrial #memory management #testing: Memory Testing Under Different Stress Conditions: An Industrial Evaluation (AKM, MA, GG, ML, SE, FB), pp. 438–443.
DATE-2005-PomeranzR #analysis #detection #testing #worst-case: Worst-Case and Average-Case Analysis of n-Detection Test Sets (IP, SMR), pp. 444–449.
DATE-2005-TangCRWRP #fault: Defect Aware Test Patterns (HT, GC, SMR, CW, JR, IP), pp. 450–455.
DATE-2005-LiauS: Computational Intelligence Characterization Method of Semiconductor Device (EL, DSL), pp. 456–461.
DATE-2005-LopezPN #embedded #metric: A New Embedded Measurement Structure for eDRAM Capacitor (LL, JMP, DN), pp. 462–463.
DATE-2005-BotaRRS #testing: Smart Temperature Sensor for Thermal Testing of Cell-Based ICs (SAB, MR, JLR, JS), pp. 464–465.
DATE-2005-YangCK #algorithm #approximate #energy #multi #scheduling: An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor (CYY, JJC, TWK), pp. 468–473.
DATE-2005-WuRJ #energy #realtime #scheduling: Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model (HW, BR, EDJ), pp. 474–479.
DATE-2005-HeniaE #analysis #distributed #scheduling: Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies (RH, RE), pp. 480–485.
DATE-2005-ChakrabortyT #analysis #scheduling #streaming: A New Task Model for Streaming Applications and Its Schedulability Analysis (SC, LT), pp. 486–491.
DATE-2005-AlbersS #analysis #performance #realtime #scheduling: Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling (KA, FS), pp. 492–497.
DATE-2005-HaiYC #modelling #realtime: Unified Modeling of Complex Real-Time Control Systems (HH, ZYf, CCl), pp. 498–499.
DATE-2005-MarconCMSRH #energy: Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique (CAMM, NLVC, FGM, AAS, IMR, FH), pp. 502–507.
DATE-2005-LoghiP #energy #memory management #performance #trade-off: Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions (ML, MP), pp. 508–513.
DATE-2005-AndreiSEPH #constraints #energy #scalability: Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints (AA, MTS, PE, ZP, BMAH), pp. 514–519.
DATE-2005-LoghiAP #architecture #energy: Tag Overflow Buffering: An Energy-Efficient Cache Architecture (ML, PA, MP), pp. 520–525.
DATE-2005-LiWYY #named #performance #power management: Q-DPM: An Efficient Model-Free Dynamic Power Management Technique (ML, XW, RY, XY), pp. 526–527.
DATE-2005-CoburnRR #estimation #hardware: Hardware Accelerated Power Estimation (JC, SR, AR), pp. 528–529.
DATE-2005-Sangiovanni-Vincentelli #design #evolution #question: Integrated Electronics in the Car and the Design Chain Evolution or Revolution? (ALSV), pp. 532–533.
DATE-2005-Brinkmeyer #approach #component #testing: A New Approach to Component Testing (HB), pp. 534–535.
DATE-2005-IllgenO #assurance #case study #experience #perspective #process #quality: Process Oriented Software Quality Assurance — An Experience Report in Process Improvement — OEM Perspective (TI, SO), pp. 536–537.
DATE-2005-Langenwalter #development #embedded #process: Embedded Automotive System Development Process (JL), pp. 538–539.
DATE-2005-AbdiG #functional #scheduling #validation: Functional Validation of System Level Static Scheduling (SA, DDG), pp. 542–547.
DATE-2005-ZhaoG #semantics: Defining an Enhanced RTL Semantics (SZ, DDG), pp. 548–553.
DATE-2005-HassanSTI #kernel #simulation: RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC (MAH, KS, YT, MI), pp. 554–559.
DATE-2005-HabibiT #design #modelling #transaction #verification: Design for Verification of SystemC Transaction Level Models (AH, ST), pp. 560–565.
DATE-2005-Klingauf #embedded #modelling #transaction: Systematic Transaction Level Modeling of Embedded Systems with SystemC (WK), pp. 566–567.
DATE-2005-DasguptaY #architecture #modelling #verification: Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures (SD, AY), pp. 568–569.
DATE-2005-ZorianFWESGR #industrial #question: Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? (YZ, BF, DW, JE, GS, MG, KNR), p. 572.
DATE-2005-LiTW #embedded #performance: An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories (JFL, TWT, CLW), pp. 574–579.
DATE-2005-SchianoOLPS #analysis #fault #on the #reliability: On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories (LS, MO, FL, SP, AS), pp. 580–585.
DATE-2005-MemikKO #fault: Increasing Register File Immunity to Transient Errors (GM, MTK, ÖÖ), pp. 586–591.
DATE-2005-GillNWPG #design #detection #performance: An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories (BSG, MN, FGW, CAP, SLG), pp. 592–597.
DATE-2005-WehmeyerM #embedded #memory management #predict: nfluence of Memory Hierarchies on Predictability for Time Constrained Embedded Software (LW, PM), pp. 600–605.
DATE-2005-WenzelRKP #clustering #context-free grammar #generative #model checking: utomatic Timing Model Generation by CFG Partitioning and Model Checking (IW, BR, RK, PPP), pp. 606–611.
DATE-2005-BurguiereR #branch #modelling #predict: A Contribution to Branch Prediction Modeling in WCET Analysi (CB, CR), pp. 612–617.
DATE-2005-HeckmannF #abstract interpretation #embedded #safety: erifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation (RH, CF), pp. 618–619.
DATE-2005-KhanV #algorithm #platform #scheduling: An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms (JK, RV), pp. 622–627.
DATE-2005-TiriV #constant #design #difference #logic #power management: Design Method for Constant Power Consumption of Differential Logic Circuits (KT, IV), pp. 628–633.
DATE-2005-LeungTH #energy #scheduling: Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling (LFL, CYT, XSH), pp. 634–639.
DATE-2005-VerleMAMA #optimisation #power management #protocol: Low Power Oriented CMOS Circuit Optimization Protocol (AV, XM, NA, PM, DA), pp. 640–645.
DATE-2005-KitaharaKMSF #design #multi #power management #reduction: Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction (TK, NK, FM, KS, TF), pp. 646–647.
DATE-2005-LinkV #configuration management #runtime: Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip (GML, NV), pp. 648–649.
DATE-2005-BaiKKSM #multi #trade-off: Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage (RB, NSK, TK, DS, TNM), pp. 650–651.
DATE-2005-BortolazziMBM #architecture: Automotive System Architectures (Automotive Special Day) (JB, JLM, JB, CM), p. 654.
DATE-2005-Heinecke #challenge #design: Automotive System Design — Challenges and Potential (HH), pp. 656–657.
DATE-2005-ManquinhoM #bound #effectiveness #optimisation #pseudo: Effective Lower Bounding Techniques for Pseudo-Boolean Optimization (VMM, JPMS), pp. 660–665.
DATE-2005-IyerPC #constraints #learning #performance #theorem proving: Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver (MKI, GP, KTC), pp. 666–671.
DATE-2005-ShenQL #algorithm #analysis #performance: A Faster Counterexample Minimization Algorithm Based on Refutation Analysis (SS, YQ, SL), pp. 672–677.
DATE-2005-MishraD #functional #generative #pipes and filters #testing #validation: Functional Coverage Driven Test Generation for Validation of Pipelined Processors (PM, NDD), pp. 678–683.
DATE-2005-SheiniS #named #pseudo #satisfiability: Pueblo: A Modern Pseudo-Boolean SAT Solver (HMS, KAS), pp. 684–685.
DATE-2005-KatzHD #bound #model checking: Space-Efficient Bounded Model Checking (JK, ZH, ND), pp. 686–687.
DATE-2005-CabodiCNQ #bound #model checking #quantifier #set: Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking (GC, MC, SN, SQ), pp. 688–689.
DATE-2005-SchattkowskyMR #approach #configuration management #execution #hardware #modelling #specification: A Model-Based Approach for Executable Specifications on Reconfigurable Hardware (TS, WM, AR), pp. 692–697.
DATE-2005-ChureauSA #functional #prototype #uml: The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application (AC, YS, EMA), pp. 698–703.
DATE-2005-RiccobeneSRB #design #uml: A SoC Design Methodology Involving a UML 2.0 Profile for SystemC (ER, PS, AR, SB), pp. 704–709.
DATE-2005-KukkalaRHHK #design #embedded #uml: UML 2.0 Profile for Embedded System Design (PK, JR, MH, TDH, KK), pp. 710–715.
DATE-2005-VanderperrenD #approach #complexity #design #uml: UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design (YV, WD), pp. 716–717.
DATE-2005-AhmedM #design #embedded #performance #refinement: Design Refinement for Efficient Cluste ing of Objects in Embedded Systems (WA, DM), pp. 718–719.
DATE-2005-MarinissenPKZ #challenge #design #embedded #memory management: Challenges in Embedded Memory Design and Test (EJM, BP, DKS, YZ), pp. 722–727.
DATE-2005-GangwarBPK #architecture #clustering #evaluation: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures (AG, MB, PRP, AK), pp. 730–735.
DATE-2005-FrancescoAM #architecture #distributed #flexibility #hardware #memory management #message passing: Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture (FP, AP, PM), pp. 736–741.
DATE-2005-NaculG #compilation #embedded #lightweight #multi #using: Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler (ACN, TG), pp. 742–747.
DATE-2005-BarrettaFSB #clustering #embedded #parallel #thread: Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications (DB, WF, MS, DB), pp. 748–749.
DATE-2005-LiS #performance #simulation: An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation (ZL, CJRS), pp. 752–757.
DATE-2005-SukhwaniPW #design #named #statistics: Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design (BBS, UP, JMW), pp. 758–763.
DATE-2005-KangPR #analysis #statistics #using: Statistical Timing Analysis using Levelized Covariance Propagation (KK, BCP, KR), pp. 764–769.
DATE-2005-KumarLTW #multi #probability #process #statistics: A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching (YSK, JL, CT, JMW), pp. 770–775.
DATE-2005-NazarianPTLA #analysis #modelling: Modeling and Propagation of Noisy Waveforms in Static Timing Analysis (SN, MP, ET, TL, AHA), pp. 776–777.
DATE-2005-MahadevanASOSM #generative #network #performance #simulation: A Network Traffic Generator Model for Fast Network-on-Chip Simulation (SM, FA, MS, RGO, JS, JM), pp. 780–785.
DATE-2005-ReshadiD #generative #modelling #performance #pipes and filters: Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation (MR, NDD), pp. 786–791.
DATE-2005-SchnerrBR #agile #prototype #simulation: Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs (JS, OB, WR), pp. 792–797.
DATE-2005-FummiLMMPP #hardware #prototype: Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation (FF, ML, SM, MM, GP, MP), pp. 798–803.
DATE-2005-VillaSVMP #framework #integration #memory management #multi #performance: Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip (OV, PS, IV, MM, GP), pp. 804–805.
DATE-2005-IsseninD #automation #generative #memory management #named #optimisation: FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations (II, NDD), pp. 808–813.
DATE-2005-OzturkK #energy #memory management: Nonuniform Banking for Reducing Memory Energy Consumption (ÖÖ, MTK), pp. 814–819.
DATE-2005-VargheseCY #analysis #using: Systematic Analysis of Active Clock Deskewing Systems Using Control Theory (VV, TC, PMY), pp. 820–825.
DATE-2005-KallakuriDF #communication: Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip (SK, AD, EAF), pp. 826–827.
DATE-2005-HanlaiMJ #control flow #graph #memory management #optimisation #performance #using: Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory (PH, LM, JJ), pp. 828–829.
DATE-2005-Schattkowsky #design #overview #uml: UML 2.0 — Overview and Perspectives in SoC Design (TS), pp. 832–833.
DATE-2005-MellorWM #uml #why: Why Systems-on-Chip Needs More UML like a Hole in the Head (SJM, JRW, CM), pp. 834–835.
DATE-2005-ZhuOHN #design #process #uml: Integrating UML into SoC Design Process (QZ, RO, TH, TN), pp. 836–837.
DATE-2005-RosingerAC #agile #generative: Rapid Generation of Thermal-Safe Test Schedules (PMR, BMAH, KC), pp. 840–845.
DATE-2005-SharifiJHAN #reduction: Simultaneous Reduction of Dynamic and Static Power in Scan Structures (SS, JJ, MH, AAK, ZN), pp. 846–851.
DATE-2005-WangWI #distributed #embedded #performance: A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs (BW, YW, AI), pp. 852–857.
DATE-2005-BodeanBL #ram #self: New Schemes for Self-Testing RAM (GB, DB, AL), pp. 858–859.
DATE-2005-CheonLWWHCPCW #logic: At-Speed Logic BIST for IP Cores (BC, EL, LTW, XW, PH, JC, JP, HC, SW), pp. 860–861.
DATE-2005-IzosimovPEP #design #distributed #embedded #fault tolerance #optimisation: Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems (VI, PP, PE, ZP), pp. 864–869.
DATE-2005-KandemirC #embedded #process #scheduling: Locality-Aware Process Scheduling for Embedded MPSoCs (MTK, GC), pp. 870–875.
DATE-2005-KempfDLAMKV #composition #framework #multi #platform #simulation: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms (TK, MD, RL, GA, HM, TK, BV), pp. 876–881.
DATE-2005-OzturkSKK #embedded: Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems (ÖÖ, HS, MTK, IK), pp. 882–887.
DATE-2005-MannionHCV #network #programmable #synthesis: System Synthesis for Networks of Programmable Blocks (RM, HH, SC, FV), pp. 888–893.
DATE-2005-StreichertHT #clustering #configuration management #distributed #embedded #network: Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks (TS, CH, JT), pp. 894–895.
DATE-2005-BomelMB #latency #synthesis: Synchronization Processor Synthesis for Latency Insensitive Systems (PB, EM, EB), pp. 896–897.
DATE-2005-HungXVKI #embedded #scheduling: Thermal-Aware Task Allocation and Scheduling for Embedded Systems (WLH, YX, NV, MTK, MJI), pp. 898–899.
DATE-2005-VorwerkK #framework #multi: An Improved Multi-Level Framework for Force-Directed Placement (KV, AAK), pp. 902–907.
DATE-2005-ChiangKSXZ #detection: Bright-Field AAPSM Conflict Detection and Correction (CC, ABK, SS, XX, AZ), pp. 908–913.
DATE-2005-WangMDCM #analysis #embedded #energy #process #variability: Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules (HW, MM, WD, FC, KM), pp. 914–919.
DATE-2005-AlexandreCCSME #framework #named #platform #research: TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform (CA, HC, JPC, MS, CM, RE), pp. 920–921.
DATE-2005-BhaduriV #higher-order #induction #metric: Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric (AB, RV), pp. 922–923.
DATE-2005-DattaBMBR #design #modelling #pipes and filters #process #statistics: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies (AD, SB, SM, NB, KR), pp. 926–931.
DATE-2005-MolnosHCE #communication #composition #memory management #multi: Compositional Memory Systems for Multimedia Communicating Tasks (AMM, MJMH, SDC, JTJvE), pp. 932–937.
DATE-2005-KruseTEVS #contract #design #distributed #embedded #flexibility #process: Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes (JK, CT, RE, TV, TS), pp. 938–943.
DATE-2005-CasuM #design #pipes and filters: A New System Design Methodology for Wire Pipelined SoC (MRC, LM), pp. 944–945.
DATE-2005-DasygenisBDCST #energy #memory management #performance: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck (MD, EB, BD, FC, DS, AT), pp. 946–947.
DATE-2005-RosenstielBGGKLMMMS #question #tool support: Is there a Market for SystemC Tools? (WR, RAB, FG, TG, MK, MCvL, AM, MM, MM, SS), p. 950.
DATE-2005-ZhangCHC #analysis #pseudo #statistics: Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model (LZ, WC, YH, CCPC), pp. 952–957.
DATE-2005-LiLLPN #modelling #order #parametricity #performance #reduction #using #variability: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction (PL, FL, XL, LTP, SRN), pp. 958–963.
DATE-2005-GhantaVPW #analysis #grid #power management #probability #process: Stochastic Power Grid Analysis Considering Process Variations (PG, SBKV, RP, JMW), pp. 964–969.
DATE-2005-XiongTH #process: Buffer Insertion Considering Process Variation (JX, KHT, LH), pp. 970–975.
DATE-2005-WangM #approximate #modelling: EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation (BW, PM), pp. 976–981.
DATE-2005-ForzanP #analysis #behaviour #library #modelling: Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis (CF, DP), pp. 982–983.
DATE-2005-ChandyC #interactive #performance: Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions (AC, TC), pp. 984–985.
DATE-2005-ZuberWOSH #optimisation #power management #reduction: Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization (PZ, AW, RMBdO, WS, AH), pp. 986–987.
DATE-2005-KumarTCJ #fault: Implicit and Exact Path Delay Fault Grading in Sequential Circuits (MMVK, ST, SC, RJ), pp. 990–995.
DATE-2005-YangVTV #automation #debugging #design #fault #modelling #power management: Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs (YSY, AGV, PJT, SV), pp. 996–1001.
DATE-2005-ChandrasekarH #fault #generative #incremental #integration #learning #performance #satisfiability #testing: Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation (KC, MSH), pp. 1002–1007.
DATE-2005-PomeranzR05a #detection #fault #heuristic: The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits (IP, SMR), pp. 1008–1013.
DATE-2005-SandireddyA #detection #fault #multi: Diagnostic and Detection Fault Collapsing for Multiple Output Circuits (RKKRS, VDA), pp. 1014–1019.
DATE-2005-Al-ArsHMG #analysis #fault #framework #generative #testing: Framework for Fault Analysis and Test Generation in DRAMs (ZAA, SH, GM, AJvdG), pp. 1020–1021.
DATE-2005-ScholiveBRFR #generative #testing: Mutation Sampling Technique for the Generation of Structural Test Data (MS, VB, CR, MLF, BR), pp. 1022–1023.
DATE-2005-KandemirLCCO #embedded #in memory #trade-off: Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing (MTK, FL, GC, GC, ÖÖ), pp. 1026–1031.
DATE-2005-OzturkKI #garbage collection #named: BB-GC: Basic-Block Level Garbage Collection (ÖÖ, MTK, MJI), pp. 1032–1037.
DATE-2005-CombazFLS #multi: Fine Grain QoS Control for Multimedia Application Software (JC, JCF, TL, JS), pp. 1038–1043.
DATE-2005-BaleaniFMSFSW #design #development #embedded #modelling: Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development (MB, AF, LM, ALSV, UF, ES, HJW), pp. 1044–1049.
DATE-2005-CheongL #embedded #named: galsC: A Language for Event-Driven Embedded Systems (EC, JL), pp. 1050–1055.
DATE-2005-HuLDKVI #detection #fault: Compiler-Directed Instruction Duplication for Soft Error Detection (JSH, FL, VD, MTK, NV, MJI), pp. 1056–1057.
DATE-2005-Takeuchi #debugging #lightweight #monitoring #using #virtual machine: OS Debugging Method Using a Lightweight Virtual Machine Monitor (TT), pp. 1058–1059.
DATE-2005-KavvadiasN #embedded #hardware: Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications (NK, SN), pp. 1060–1061.
DATE-2005-SomaniCP #contest #design #optimisation #search-based: Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits (AS, PPC, AP), pp. 1064–1069.
DATE-2005-EeckelaertMG #multi #performance #synthesis #using: Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces (TE, TM, GGEG), pp. 1070–1075.
DATE-2005-VandersteenLJRP #framework #modelling #scalability: Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework (GV, LDL, SJ, YR, RP), pp. 1076–1081.
DATE-2005-McConaghyEG #canonical #generative #named #programming #search-based: CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming (TM, TE, GGEG), pp. 1082–1087.
DATE-2005-DingV #approach #megamodelling #modelling #performance: A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling (MD, RV), pp. 1088–1089.
DATE-2005-ManaresiMAAVRATG: New Perspectives and Opportunities From the Wild West of Microelectronic Biochips (NM, GM, MA, VA, PV, AR, LA, MT, RG), pp. 1092–1093.
DATE-2005-GanaiGA #embedded #memory management #modelling #performance #using #verification: Verification of Embedded Memory Systems using Efficient Memory Modeling (MKG, AG, PA), pp. 1096–1101.
DATE-2005-LuIPWCC #performance #satisfiability: An Efficient Sequential SAT Solver With Improved Search Strategies (FL, MKI, GP, LCW, KTC, KCC), pp. 1102–1107.
DATE-2005-FuYM #satisfiability: Considering Circuit Observability Don’t Cares in CNF Satisfiability (ZF, YY, SM), pp. 1108–1113.
DATE-2005-ChenLL #integration #layout #multi #verification: Integration, Verification and Layout of a Complex Multimedia SOC (CLC, JYL, YLL), pp. 1116–1117.
DATE-2005-LianHFCC #development #parsing expression grammar: PEG, MPEG-4, and H.264 Codec IP Development (CJL, YWH, HCF, YCC, LGC), pp. 1118–1119.
DATE-2005-Wu #testing: SOC Testing Methodology and Practice (CWW), pp. 1120–1121.
DATE-2005-PolianCB #optimisation: Evolutionary Optimization in Code-Based Test Compression (IP, AC, BB), pp. 1124–1129.
DATE-2005-BalakrishnanT #configuration management #linear #using: Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination (KJB, NAT), pp. 1130–1135.
DATE-2005-BhuniaMRR #novel #testing: A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application (SB, HMM, AR, KR), pp. 1136–1141.
DATE-2005-LiC #analysis #clustering #hybrid #sequence: Hybrid BIST Based on Repeating Sequences and Cluster Analysis (LL, KC), pp. 1142–1147.
DATE-2005-CengHLAMB #c #compilation #modelling #semantics: C Compiler Retargeting Based on Instruction Semantics Models (JC, MH, RL, GA, HM, GB), pp. 1150–1155.
DATE-2005-ChenKK #approach #constraints #layout #memory management #network #optimisation: A Constraint Network Based Approach to Memory Layout Optimization (GC, MTK, MK), pp. 1156–1161.
DATE-2005-AbsarC #approach #array: Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access (MJA, FC), pp. 1162–1167.
DATE-2005-Dubrova #kernel #testing: Structural Testing Based on Minimum Kernels (ED), pp. 1168–1173.
DATE-2005-MuraliM #design #generative: An Application-Specific Design Methodology for STbus Crossbar Generation (SM, GDM), pp. 1176–1181.
DATE-2005-GoossensDGPRR #design #network #performance #verification: A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification (KG, JD, OPG, SGP, AR, ER), pp. 1182–1187.
DATE-2005-StergiouACRBM #abstract syntax tree #design #library #network #pipes and filters #synthesis: ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips (SS, FA, SC, LR, DB, GDM), pp. 1188–1193.
DATE-2005-SuCP #configuration management #using: Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration (FS, KC, VKP), pp. 1196–1201.
DATE-2005-SuC #configuration management #design #fault tolerance: Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips (FS, KC), pp. 1202–1207.
DATE-2005-MaslovYMD #quantum #using: Quantum Circuit Simplification Using Templates (DM, CY, DMM, GWD), pp. 1208–1213.
DATE-2005-KimWK #architecture #design #robust: owards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths (KK, KW, RK), pp. 1214–1219.
DATE-2005-ThewesPSHFBAJESAHBHH #array: CMOS-Based Biosensor Arrays (RT, CP, MS, FH, AF, RB, MA, MJ, BE, PSB, MA, BH, GB, TH, HCH), pp. 1222–1223.
DATE-2005-BjerregaardS #architecture: A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip (TB, JS), pp. 1226–1231.
DATE-2005-WeberCSW #network: A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips (WDW, JC, IS, DW), pp. 1232–1237.
DATE-2005-WangPM #energy #network: A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks (HW, LSP, SM), pp. 1238–1243.
DATE-2005-BiswasBDPI #generative #named #set: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement (PB, SB, NDD, LP, PI), pp. 1246–1251.
DATE-2005-Ruiz-SautuaMMH #behaviour #performance #synthesis: Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis (RRS, MCM, JMM, RH), pp. 1252–1257.
DATE-2005-TosunMAKX #synthesis: Reliability-Centric High-Level Synthesis (ST, NM, EA, MTK, YX), pp. 1258–1263.
DATE-2005-ShrivastavaDNE #embedded #framework #named: PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors (AS, NDD, AN, EE), pp. 1264–1269.
DATE-2005-AlmukhaizimM #concurrent #detection #fault: Concurrent Error Detection in Asynchronous Burst-Mode Controllers (SA, YM), pp. 1272–1277.
DATE-2005-BolchiniSSP #reliability #self #specification: Reliable System Specification for Self-Checking Data-Paths (CB, FS, DS, LP), pp. 1278–1283.
DATE-2005-HashempourSL #evaluation #reliability #testing: Evaluation of Error-Resilience for Reliable Compression of Test Data (HH, LS, FL), pp. 1284–1289.
DATE-2005-KastensmidtSCR #composition #design #logic #on the: On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs (FLK, LS, LC, MSR), pp. 1290–1295.
DATE-2005-JacobiWPB #automation #multi #verification: Automatic Formal Verification of Fused-Multiply-Add FPUs (CJ, KW, VP, JB), pp. 1298–1303.
DATE-2005-ManoliosS #modelling #performance #refinement #verification: Refinement Maps for Efficient Verification of Processor Models (PM, SKS), pp. 1304–1309.
DATE-2005-ShashidharBCJ #algebra #equivalence #functional #source code #verification: Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code (KCS, MB, FC, GJ), pp. 1310–1315.
DATE-2005-LaMeresK #encoding #induction: Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission (BJL, SPK), pp. 1318–1323.
DATE-2005-LiS05a #algorithm: An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types (ZL, WS), pp. 1324–1329.
DATE-2005-LiuPP #hybrid #named #performance #power management: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power (XL, YP, MCP), pp. 1330–1335.
DATE-2005-Campagnolo #detection #generative: eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical Detection (RC), pp. 1338–1339.
DATE-2005-KirsteinLZVVSLH: Cantilever-Based Biosensors in CMOS Technology (KUK, YL, MZ, CV, TV, WHS, JL, AH), pp. 1340–1341.

Proceedings of the Ninth Conference on Design, Automation and Test in EuropeDATE, 2005.

Contents (312 items)

Proceedings of the Ninth Conference on Design, Automation and Test in Europe
DATE, 2005.