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Travelled to:
1 × Germany
Collaborated with:
O.Barondeau M.Kaibel F.Poehl X.Lin R.Press
Talks about:
test (2) implement (1) qualiti (1) generat (1) impact (1) detail (1) design (1) logic (1) delay (1) clock (1)

Person: Matthias Beck

DBLP DBLP: Beck:Matthias

Contributed to:

DATE 20052005

Wrote 1 papers:

DATE-2005-BeckBKPLP #design #generative #implementation #logic #quality
Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality (MB, OB, MK, FP, XL, RP), pp. 56–61.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.