BibSLEIGH — Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality

Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press
Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality
DATE, 2005.

DATE 2005

@inproceedings{DATE-2005-BeckBKPLP,
	author        = "Matthias Beck and Olivier Barondeau and Martin Kaibel and Frank Poehl and Xijiang Lin and Ron Press",
	booktitle     = "{Proceedings of the Ninth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.2005.199",
	isbn          = "0-7695-2288-2",
	pages         = "56--61",
	publisher     = "{IEEE Computer Society}",
	title         = "{Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality}",
	year          = 2005,
}

Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron PressLogic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test QualityDATE, 2005.

Tags:

Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press
Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality
DATE, 2005.