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Travelled to:
1 × USA
Collaborated with:
A.Chlipala Arvind N.Dave
Talks about:
multiprocessor (1) modular (1) hardwar (1) design (1) deduct (1) verif (1)

Person: Muralidaran Vijayaraghavan

DBLP DBLP: Vijayaraghavan:Muralidaran

Contributed to:

CAV 20152015

Wrote 1 papers:

CAV-2015-VijayaraghavanC #composition #deduction #design #hardware #multi #verification
Modular Deductive Verification of Multiprocessor Hardware Designs (MV, AC, A, ND), pp. 109–127.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.