BibSLEIGH — Proceedings of the 22nd Design Automation Conference

Hillel Ofek, Lawrence A. O'Neill
Proceedings of the 22nd Design Automation Conference
DAC, 1985.

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@proceedings{DAC-1985,
	acmid         = "317825",
	address       = "Las Vegas, Nevada, USA",
	editor        = "Hillel Ofek and Lawrence A. O'Neill",
	isbn          = "0-8186-0635-5",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 22nd Design Automation Conference}",
	year          = 1985,
}

Contents (132 items)

DAC-1985-SamadD #interface #natural language #towards: Towards a natural language interface for CAD (TS, SWD), pp. 2–8.
DAC-1985-JanniI #user interface: Unified user interface for a CAD system (ADJ, MI), pp. 9–15.
DAC-1985-BamjiHA #design #generative: A design by example regular structure generator (CB, CEH, JA), pp. 16–22.
DAC-1985-HughesLR #automation #design #distributed #execution #tool support: A technique for distributed execution of design automation tools (SCH, DBL, CJR), pp. 23–30.
DAC-1985-YoffaH #approach #design #named #physics: ACORN: a local customization approach to DCVS physical design (EJY, PSH), pp. 32–38.
DAC-1985-NgJ #approach #generative #graph: Generation of layouts from MOS circuit schematics: a graph theoretic approach (TKN, SLJ), pp. 39–45.
DAC-1985-NodaYFKKF #algorithm #array #automation #layout: Automatic layout algorithms for function blocks of CMOS gate arrays (SN, HY, EF, HK, HK, TF), pp. 46–52.
DAC-1985-SaucierT #layout: Systematic and optimized layout of MOS cells (GS, GT), pp. 53–61.
DAC-1985-RogersRD #design: MCNC’s vertically integrated symbolic design system (CDR, JBR, SWD), pp. 62–68.
DAC-1985-EntenmanD #automation: A fully automatic hierarchical compactor (GE, SWD), pp. 69–75.
DAC-1985-SmtihD #approach #file system #independence: The VIVID system approach to technology independence: the matster technology file system (PS, SWD), pp. 76–81.
DAC-1985-Rosenberg #layout: Auto-interactive schematics to layout translation (JBR), pp. 82–87.
DAC-1985-LowensteinW #standard: Importance of standards (AL, GW), pp. 88–93.
DAC-1985-PierroD #analysis #design #integration: Mechanical design/analysis integration on Apollo workstations (JAP, GFD), pp. 96–101.
DAC-1985-Abraham #optimisation: Custom microcomputers for CAD optimization software (RA), pp. 102–110.
DAC-1985-Kalay #approach #database #integration: A database management approach to CAD/CAM systems integration (YEK), pp. 111–116.
DAC-1985-Marek-Sadowska #2d #layout: Two-dimensional router for double layer layout (MMS), pp. 117–123.
DAC-1985-BursteinY #design #layout: Timing influenced layout design (MB, MNY), pp. 124–130.
DAC-1985-SongC #algorithm: An algorithm for one and half layer channel routing (JNS, YKC), pp. 131–136.
DAC-1985-HennionSC #algorithm #generative: A new algorithm for third generation circuit simulators: the one-step relaxation method (BH, PS, DC), pp. 137–143.
DAC-1985-Matson #megamodelling: Macromodeling of digital MOS VLSI Circuits (MDM), pp. 141–151.
DAC-1985-MuraokaIKMH #analysis #named: ACTAS: an accurate timing analysis system for VLSI (MM, HI, HK, MM, KH), pp. 152–158.
DAC-1985-Simmons #design #prototype #verification: Early verification of prototype tooling for IC designs (JPSJ), p. 161.
DAC-1985-HealeyG #composition #logic #network: Decomposition of logic networks into silicon (STH, DDG), pp. 162–168.
DAC-1985-RowenH #flexibility #implementation #logic #named: SWAMI: a flexible logic implementation system (CR, JLH), pp. 169–175.
DAC-1985-KrekelbergSJ #compilation: Yet another silicon compiler (DEK, GES, CSJ), pp. 176–182.
DAC-1985-Mata #named #specification: ALLENDE: a procedural language for the hierarchical specification of VLSI layouts (JMdM), pp. 183–189.
DAC-1985-FungHK #compilation #design #testing: Design for testability in a silicon compilation environment (HSF, SH, RK), pp. 190–196.
DAC-1985-WeiS #generative #named: PLATYPUS: a PLA test pattern generation tool (RSW, ALSV), pp. 197–203.
DAC-1985-Wunderlich #analysis #named #probability #testing: PROTEST: a tool for probabilistic testability analysis (HJW), pp. 204–211.
DAC-1985-OgiharaSM #automation #generative #named #parametricity #testing: PATEGE: an automatic DC parametric test generation system for series gated ECL circuits (TO, SS, SM), pp. 212–218.
DAC-1985-Frome #tutorial #video: Course, video, and manual dexterity (tutorial): tailoring training to CAD users (FSF), pp. 226–231.
DAC-1985-BlackmanFR #compilation: The Silc silicon compiler: language and features (TB, JRF, CR), pp. 232–237.
DAC-1985-MeshkinpourE #design #functional: A functional language for description and design of digital systems: sequential constructs (FM, MDE), pp. 238–244.
DAC-1985-Cory #layout #named: Layla: a VLSI layout language (WEC), pp. 245–251.
DAC-1985-KowalskiT #automation #design #knowledge base #what: The VLSI design automation assistant: what’s in a knowledge base (TJK, DET), pp. 252–258.
DAC-1985-BreuerZ #knowledge base: A knowledge based system for selecting a test methodology for a PLA (MAB, XaZ), pp. 259–265.
DAC-1985-JoobbaniS #knowledge-based #named: WEAVER: a knowledge-based routing expert (RJ, DPS), pp. 266–272.
DAC-1985-Bergmann #design #independence: Generalised CMOS-a technology independent CMOS IC design style (NB), pp. 273–278.
DAC-1985-ChuL #design #layout #tool support: Technology tracking for VLSI layout design tools (KCC, YEL), pp. 279–285.
DAC-1985-ScottO: Magic’s circuit extractor (WSS, JKO), pp. 286–292.
DAC-1985-SchefferS #abstraction #analysis: Hierarchical analysis of IC artwork with user defined abstraction rules (LS, RS), pp. 293–298.
DAC-1985-BierP #algorithm #design #multi: An algorithm for design rule checking on a multiprocessor (GEB, ARP), pp. 299–304.
DAC-1985-Barke #finite: Resistance calculation from mask artwork data by finite element method (EB), pp. 305–311.
DAC-1985-Smith #architecture #design #nondeterminism: A data architecture for an uncertain design and manufacturing environment (TRS), pp. 312–318.
DAC-1985-Strojwas: CMU-CAM system (AJS), pp. 319–325.
DAC-1985-Reid-Green #effectiveness #prototype: Cost-effective computer-aided manufacturing of prototype parts (KSRG), pp. 326–329.
DAC-1985-ChangW #assembly #knowledge base: A knowledge based planning system for mechanical assembly usign robots (KHC, WGW), pp. 330–336.
DAC-1985-TaylorBS #design #layout #lessons learnt: Layout design-lessons from the Jedi designer (SLT, RB, TS), p. 337.
DAC-1985-HahnF #music #named #performance #simulation: MuSiC: an event-flow computer for fast simulation of digital systems (WH, KF), pp. 338–344.
DAC-1985-Lewis #hardware #simulation: A hardware engine for analogue mode simulation of MOS digital circuits (DML), pp. 345–351.
DAC-1985-HefferanSBN: The STE-264 accelerated electronic CAD system (PMH, RJSI, VB, DLN), pp. 352–358.
DAC-1985-SpiraH #array #hardware #layout: Hardware acceleration of gate array layout (PMS, CH), pp. 359–366.
DAC-1985-RajanT #synthesis: Synthesis by delayed binding of decisions (JVR, DET), pp. 367–373.
DAC-1985-BlackburnT #behaviour #representation #synthesis: Linking the behavioral and structural dominis of representation in a synthesis system (RLB, DET), pp. 374–380.
DAC-1985-RamayyaKP #automation #canonical: An automated data path synthesizer for a canonic structure, implementable in VLSI (KR, AK, SP), pp. 381–387.
DAC-1985-AryaKSM #automation #diagrams #generative: Automatic generation of digital system schematic diagrams (AA, AK, VVS, AM), pp. 388–395.
DAC-1985-Cho #overview: A subjective review of compaction (YEC), pp. 396–404.
DAC-1985-WayneB: Looking for Mr. “Turnkey” (MRW, SMB), pp. 405–409.
DAC-1985-WinslettBPW #database #design #relational: Relational and entity-relationship model databases and specialized design files in VLSI design (MW, RB, THP, GW), pp. 410–416.
DAC-1985-SmithFC #architecture #assessment #design #hardware: An architecture design and assessment system for software/hardware codesign (CUS, GAF, JLC), pp. 417–424.
DAC-1985-PerryMP #analysis #modelling: Yield analysis modeling (SP, MM, DJP), pp. 425–428.
DAC-1985-SakataK #comparison #linear: A circuit comparison system for bipolar linear LSI (TS, AK), pp. 429–434.
DAC-1985-SteinwegAPN #array #compilation: Silicon compilation of gate array bases (RLS, SJA, KP, SN), pp. 435–438.
DAC-1985-IachponiVBI #architecture #array #design: A hierarchical gate array architecture and design methodology (MI, DV, SB, AI), pp. 439–442.
DAC-1985-HsuTCPT #layout #named #standard: ALPS2: a standard cell layout system for double-layer metal technology (CPH, BNT, KC, RAP, JT), pp. 443–448.
DAC-1985-AnwayFR #layout: PLINT layout system for VLSI chips (HA, GF, RR), pp. 449–452.
DAC-1985-WalkerT #design #representation #synthesis: A model of design representation and synthesis (RAW, DET), pp. 453–459.
DAC-1985-GiambiasiMLdDR #adaptation #modelling: An adaptive and evolutive tool for describing general hierarchical models, based on frames and demons (NG, BM, RL, LDd, CD, PR), pp. 460–467.
DAC-1985-AlthoffS #behaviour #compilation #modelling: A behavioral modeling system for cell compilers (JCA, RDS), pp. 468–474.
DAC-1985-Camposano #design #synthesis: Synthesis techniques for digital systems design (RC), pp. 475–481.
DAC-1985-RoseBT #analysis #design #performance #probability #tool support: Integrating stochastic performance analysis with system design tools (CWR, MB, YT), pp. 482–488.
DAC-1985-ParkP #synthesis: Synthesis of optimal clocking schemes (NP, ACP), pp. 489–495.
DAC-1985-CollinsK #programmable #tutorial: The impact of technological advances on programmable controller s(tutorial session) (RPC, WJK), pp. 498–502.
DAC-1985-TeraiHK #array #metaprogramming #standard: A routing procedure for mixed array of custom macros and standard cells (HT, MH, TK), pp. 503–508.
DAC-1985-FinchMBS: A method for gridless routing of printed circuit boards (ACF, KJM, GJB, GS), pp. 509–515.
DAC-1985-HanS #algorithm: Layering algorithms for single row routing (SH, SS), pp. 516–522.
DAC-1985-Joseph #approach: An expert systems approach to completing partially routed printed circuit boards (RLJ), pp. 523–528.
DAC-1985-BudneyH #design #named: MIDAS: integrated CAD for total system design (WMB, SKH), pp. 529–535.
DAC-1985-SuzukiTSK #design: Integrated design system for supercomputer SX-1/SX-2 (SS, KT, TS, MK), pp. 536–542.
DAC-1985-HutchingsBF: Integrated VLSI CAD systems at Digital Equipment Corporation (AFH, RJB, WMF), pp. 543–548.
DAC-1985-EliasBCM #design #integration #multi: The ITT VLSI design system: CAD integration in a multi-national environment (NJE, RJB, ADC, RMM), pp. 549–553.
DAC-1985-Grinthal #assurance #quality: Software quality assurance for CAD (ETG), pp. 555–561.
DAC-1985-PidgeonF #design #development #quality: Development concerns for a software design quality expert system (CWP, PAF), pp. 562–568.
DAC-1985-Schutzman #automation #database #design #named: ICHABOD: a data base manager for design automation applications (HBS), pp. 569–576.
DAC-1985-BarabinoBBM #data access: A module for improving data access and management in an integrated CAD environment (GPB, GSB, GB, MM), pp. 577–583.
DAC-1985-GoatesHSH #design: Star’s envoling design environment: a user’s perspective on CAE (GBG, PMH, RJSI, RH), pp. 584–590.
DAC-1985-RoyalHB #case study #independence #process: A case study in process independence (NR, JH, IB), pp. 591–596.
DAC-1985-GrayH: Portability in silicon CAE (JPG, JH), pp. 597–601.
DAC-1985-ShaD #algorithm: An analytical algorithm for placement of arbitrarily sized rectangular blocks (LS, RWD), pp. 602–608.
DAC-1985-Blanks #polynomial #using: Near-optimal placement using a quadratic objective function (JPB), pp. 609–615.
DAC-1985-OdawaraIW #knowledge-based: Knowledge-based placement technique for printed wiring boards (GO, KI, KW), pp. 616–622.
DAC-1985-RoyDCG #object-oriented: An object-oriented swicth-level simulator (CR, LPD, EC, JG), pp. 623–629.
DAC-1985-LathropK #functional #object-oriented #simulation: An extensible object-oriented mixed-mod functional simulation system (RHL, RSK), pp. 630–636.
DAC-1985-AshokCS #data flow #modelling #simulation #using: Modeling switch-level simulation using data flow (VA, RLC, PS), pp. 637–644.
DAC-1985-ZaraH #automation #database #design: Building a layered database for design automation (RVZ, DRH), pp. 645–651.
DAC-1985-McLellan #data transformation #design #effectiveness: Effective data management for VLSI design (PM), pp. 652–657.
DAC-1985-SchellM #algorithm #development #named: CADTOOLS: a CAD algorithm development system (ES, MRM), pp. 658–666.
DAC-1985-DagenaisAR #logic: The McBOOLE logic minimizer (MD, VKA, NCR), pp. 667–673.
DAC-1985-AgrawalAB #multi: Multiple output minimization (PA, VDA, NNB), pp. 674–680.
DAC-1985-Hedlund #optimisation: Electrical optimization of PLAs (KSH), pp. 681–687.
DAC-1985-Bryant #representation #using #visual notation: Symbolic manipulation of Boolean functions using a graphical representation (REB), pp. 688–694.
DAC-1985-Wong #verification: Hierarchical circuit verification (YW), pp. 695–701.
DAC-1985-TygarE #comparison #performance #using: Efficient netlist comparison using hierarchy and randomization (JDT, RE), pp. 702–708.
DAC-1985-Tendolkar #analysis #fault #random: Analysis of timing failures due to random AC defects in VLSI modules (NNT), pp. 709–714.
DAC-1985-BryantS #concurrent #evaluation #fault #performance: Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator (REB, MDS), pp. 715–719.
DAC-1985-GuptaA #fault #functional #modelling #simulation: Functional fault modeling and simulation for VLSI devices (AKG, JRA), pp. 720–726.
DAC-1985-GranackiKP #automation #design #interface #natural language #overview: The ADAM advanced design automation system: overview, planner and natural language interface (JJG, DK, ACP), pp. 727–730.
DAC-1985-OdawaraTO #data flow #diagrams: Diagrammatic function description of microprocessor and data-flow processor (GO, MT, IO), pp. 731–734.
DAC-1985-Frank #data-driven #simulation #using: Switch-level simulation of VLSI using a special-purpose data-driven computer (EHF), pp. 735–738.
DAC-1985-LaarhovenAD #algorithm #logic: PHIPLA-a new algorithm for logic minimization (PJMvL, EHLA, MD), pp. 739–743.
DAC-1985-KuoCH #algorithm #heuristic: A heuristic algorithm for PLA block folding (YSK, CC, TCH), pp. 744–747.
DAC-1985-NaharSS: Experiments with simulated annealing (SN, SS, ES), pp. 748–752.
DAC-1985-ZaraRNS #automaton #data type #functional #modelling: An abstract machine data structure for non-procedural functional models (RVZ, KR, GN, HS), pp. 753–756.
DAC-1985-MokkaralaFA #approach #functional #simulation #verification: A unified approach to simulation and timing verification at the functional level (VRM, AF, RA), pp. 757–761.
DAC-1985-Schaefer: A transistor-level logic-with-timing simulator for MOS circuits (TJS), pp. 762–765.
DAC-1985-KosekiY #design #named: PLAYER: a PLA design system for VLSI’s (YK, TY), pp. 766–769.
DAC-1985-DwyerMBG #array #automation #design #integration: The integration of an advanced gate array router into a fully automated design system (RD, SM, EB, DG), pp. 770–772.
DAC-1985-Lemaire #design #named #performance #process #prototype #testing: GAMMA: a fast prototype design, build, and test process (LTL), pp. 773–776.
DAC-1985-HillFL #effectiveness #generative #grid #using: Effective use of virtual grid compaction in macro-module generators (DDH, JPF, MDPL), pp. 777–780.
DAC-1985-KaoFL #algorithm #automation: Algorithms for automatic transistor sizing in CMOS digital circuits (WHK, NF, CHL), pp. 781–784.
DAC-1985-AndouYMKSH #algorithm #automation: Automatic routing algorithm for VLSI (HA, IY, YM, YK, KS, KH), pp. 785–788.
DAC-1985-VlierbergheRH #generative: Symbolic hierarchical artwork generation system (SvV, JR, WH), pp. 789–793.
DAC-1985-ChowdhuryB: The construction of minimal area power and ground nets for VLSI circuits (SUC, MAB), pp. 794–797.
DAC-1985-ObermeierK #approach: PLA driver selection: an analytic approach (FWO, RHK), pp. 798–802.
DAC-1985-ShteingartNG #automation #generative #named: RTG: automatic register level test generator (SS, AWN, JG), pp. 803–807.
DAC-1985-KrasniewskiA #estimation #self: Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications (AK, AA), pp. 808–811.
DAC-1985-MiyoshiKTNA #logic #simulation: Speed up techniques of logic simulation (MM, YK, OT, YN, NA), pp. 812–815.
DAC-1985-Chan #analysis #development #multi #network: Development of a timing analysis program for multiple clocked network (EC), pp. 816–819.
DAC-1985-DelormeRdGLMC #clustering #functional #generative #sequence #testing: A functional partitioning expert system for test sequences generation (CD, PR, LDd, NG, RL, BM, RC), pp. 820–824.
DAC-1985-ReddyRA #generative #testing: Transistor level test generation for MOS circuits (MKR, SMR, PA), pp. 825–828.
DAC-1985-Tucker #evolution: Electronic CAD/CAM-is it revolution or evolution (BWT), pp. 830–834.

Hillel Ofek, Lawrence A. O'NeillProceedings of the 22nd Design Automation ConferenceDAC, 1985.

Contents (132 items)

Hillel Ofek, Lawrence A. O'Neill
Proceedings of the 22nd Design Automation Conference
DAC, 1985.