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Travelled to:
1 × France
Collaborated with:
O.Mitea M.Meissner L.Hedrich
Talks about:
constraint (1) synthesi (1) topolog (1) circuit (1) driven (1) analog (1) autom (1)

Person: P. Jores

DBLP DBLP: Jores:P=

Contributed to:

DATE 20112011

Wrote 1 papers:

DATE-2011-MiteaMHJ #automation #constraints #synthesis
Automated constraint-driven topology synthesis for analog circuits (OM, MM, LH, PJ), pp. 1662–1665.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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