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Travelled to:
1 × France
1 × Germany
Collaborated with:
M.Meissner L.Hedrich L.Luy P.Jores
Talks about:
synthesi (2) circuit (2) analog (2) constraint (1) framework (1) isomorph (1) topolog (1) driven (1) graph (1) autom (1)

Person: Oliver Mitea

DBLP DBLP: Mitea:Oliver

Contributed to:

DATE 20122012
DATE 20112011

Wrote 2 papers:

DATE-2012-MeissnerMLH #framework #graph #morphism #performance #synthesis #testing
Fast isomorphism testing for a graph-based analog circuit synthesis framework (MM, OM, LL, LH), pp. 757–762.
DATE-2011-MiteaMHJ #automation #constraints #synthesis
Automated constraint-driven topology synthesis for analog circuits (OM, MM, LH, PJ), pp. 1662–1665.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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