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Collaborated with:
H.T.Ma S.Devadas A.L.Sangiovanni-Vincentelli
Talks about:
implement (1) algorithm (1) parallel (1) verif (1) logic (1)

Person: R. Wei

DBLP DBLP: Wei:R=

Contributed to:

DAC 19871987

Wrote 1 papers:

DAC-1987-MaDSW #algorithm #implementation #logic #parallel #verification
Logic Verification Algorithms and Their Parallel Implementation (HKTM, SD, ALSV, RW), pp. 283–290.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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