BibSLEIGH — Srinivas

Travelled to:

1 × Brazil
1 × France
1 × Italy
1 × Spain
1 × Turkey
20 × USA

Collaborated with:

K.Keutzer A.R.Newton G.E.Suh S.Y.Liao S.Malik M.v.Dijk F.Fallah ∅ P.Ashar A.Ghosh S.Hanono D.E.Clarke O.Khan H.T.Ma G.Hadjiyiannis P.Jain L.Rudolph V.Bhagwati B.Gassend A.R.Wang G.Kurian S.W.K.Tjiang A.L.Sangiovanni-Vincentelli C.W.Fletcher L.Ren X.Yu M.Burnside R.L.Rivest P.Russo A.Sudarsanam J.C.Monteiro B.Lin K.Cheng M.A.Kinsy I.Celanovic L.F.G.Sarmenta J.Rhodes J.W.Lee D.Zhang D.Chiou J.Monteiro A.Mauskar J.White R.Wei A.Kwon G.Bezerra A.Pavlo M.Stonebraker S.Raman A.Wang V.Ganesh C.W.O'Donnell M.Soos M.C.Rinard A.Solar-Lezama T.Mills A.Maywah D.Braun J.L.Burns K.Mayaram F.Romeo H.Hoffmann J.Holt E.Lau M.Maggio J.E.Miller S.M.Neuman M.E.Sinangil Y.Sinangil A.Agarwal A.P.Chandrakasan

Talks about:

sequenti (8) verif (8) generat (7) circuit (7) logic (6) base (6) synthesi (5) control (4) memori (4) effici (4)

Person: Srinivas Devadas

DBLP: Devadas:Srinivas

Facilitated 1 volumes:

Contributed to:

2015

2014

2013

2012

2008

2007

2004

2003

2002

2000

1999

1998

1997

1996

1995

1994

1992

1991

1990

1989

1987

1986

Wrote 45 papers:

ASPLOS-2015-FletcherRKDD #ram #recursion #verification: Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM (CWF, LR, AK, MvD, SD), pp. 103–116.
VLDB-2015-YuBPDS14 #concurrent #evaluation: Staring into the Abyss: An Evaluation of Concurrency Control with One Thousand Cores (XY, GB, AP, SD, MS), pp. 209–220.
HPCA-2014-FletcherRYDKD #information management #performance #ram #trade-off: Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs (CWF, LR, XY, MvD, OK, SD), pp. 213–224.
HPCA-2014-KurianDK #replication: Locality-aware data replication in the Last-Level Cache (GK, SD, OK), pp. 1–12.
DATE-2013-KinsyCKD #architecture #grid #named #smarttech: MARTHA: architecture for control and emulation of power electronics and smart grid systems (MAK, IC, OK, SD), pp. 519–524.
DAC-2012-HoffmannHKLMMNSSACD #self: Self-aware computing in the Angstrom processor (HH, JH, GK, EL, MM, JEM, SMN, MES, YS, AA, APC, SD), pp. 259–264.
SAT-2012-GaneshOSDRS #named #problem #satisfiability: Lynx: A Programmatic SAT Solver for the RNA-Folding Problem (VG, CWO, MS, SD, MCR, ASL), pp. 143–156.
SAC-2008-SarmentaDRD: Offline count-limited certificates (LFGS, MvD, JR, SD), pp. 2145–2152.
DAC-2007-SuhD #authentication #generative #physics: Physical Unclonable Functions for Device Authentication and Secret Key Generation (GES, SD), pp. 9–14.
ASPLOS-2004-SuhLZD #data flow #execution #information management: Secure program execution via dynamic information flow tracking (GES, JWL, DZ, SD), pp. 85–96.
DAC-2003-JainSD #embedded: Embedded intelligent SRAM (PJ, GES, SD), pp. 869–874.
HPCA-2003-GassendSCDD #memory management #performance #verification: Caches and Hash Trees for Efficient Memory Integrity Verification (BG, GES, DEC, MvD, SD), pp. 295–306.
SAC-2003-GassendCDD #authentication: Delay-Based Circuit Authentication and Applications (BG, DEC, MvD, SD), pp. 294–301.
SAC-2003-RamanCBDR #network #pervasive #resource management: Access-Controlled Resource Discovery for Pervasive Networks (SR, DEC, MB, SD, RLR), pp. 338–345.
HPCA-2002-SuhDR #clustering #memory management #monitoring #scheduling: A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning (GES, SD, LR), pp. 117–128.
SAC-2002-BurnsideCMMDR #mobile #protocol #security: Proxy-based security protocols in networked mobile devices (MB, DEC, TM, AM, SD, RLR), pp. 265–272.
DAC-2000-ChiouJRD #embedded #memory management #using: Application-specific memory management for embedded systems using software-controlled caches (DC, PJ, LR, SD), pp. 416–419.
DAC-1999-FallahAD #generative #simulation: Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage (FF, PA, SD), pp. 666–671.
DAC-1999-HadjiyiannisRD #architecture #evaluation #performance: A Methodology for Accurate Performance Evaluation in Architecture Exploration (GH, PR, SD), pp. 927–932.
DAC-1998-FallahDK #functional #generative #linear #modelling #programming #satisfiability #using: Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability (FF, SD, KK), pp. 528–533.
DAC-1998-FallahDK98a #functional #metric #named #performance #test coverage #verification: OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification (FF, SD, KK), pp. 152–157.
DAC-1998-HanonoD #code generation #resource management #scheduling: Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator (SH, SD), pp. 510–515.
DAC-1997-HadjiyiannisHD #named #set: ISDL: An Instruction Set Description Language for Retargetability (GH, SH, SD), pp. 299–302.
DAC-1997-LiaoD #bound #problem #using: Solving Covering Problems Using LPR-Based Lower Bounds (SYL, SD), pp. 117–120.
DAC-1997-SudarsanamLD #analysis #architecture #evaluation: Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures (AS, SYL, SD), pp. 287–292.
DAC-1996-MonteiroDAM #power management #scheduling: Scheduling Techniques to Enable Power Management (JM, SD, PA, AM), pp. 349–352.
DAC-1995-DevadasM #optimisation #overview #power management: A Survey of Optimization Techniques Targeting Low Power VLSI Circuits (SD, SM), pp. 242–247.
DAC-1995-LiaoDKTW #embedded #optimisation: Code Optimization Techniques for Embedded DSP Microprocessors (SYL, SD, KK, SWKT, ARW), pp. 599–604.
PLDI-1995-LiaoDKTW: Storage Assignment to Decrease Code Size (SYL, SD, KK, SWKT, AW), pp. 186–195.
DAC-1994-BhagwatiD #automation #pipes and filters #verification: Automatic Verification of Pipelined Microprocessors (VB, SD), pp. 603–608.
DAC-1994-MonteiroDL #estimation #logic #performance #process: A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits (JCM, SD, BL), pp. 12–17.
DAC-1992-DevadasKMW #logic #verification: Certified Timing Verification and the Transition Delay of a Logic Circuit (SD, KK, SM, ARW), pp. 549–555.
DAC-1992-GhoshDKW #estimation #process: Estimation of Average Switching Activity in Combinational and Sequential Circuits (AG, SD, KK, JW), pp. 253–259.
DAC-1991-ChengDK #design #generative #robust #standard #synthesis #testing: Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology (KTC, SD, KK), pp. 80–86.
DAC-1991-DevadasKM #algorithm #generative #multi #testing: A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults (SD, KK, SM), pp. 359–365.
DAC-1990-AsharDN #approach #composition: A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines (PA, SD, ARN), pp. 601–606.
DAC-1990-DevadasK #logic #optimisation #robust #synthesis: Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits (SD, KK), pp. 221–227.
DAC-1990-GhoshDN #verification: Verification of Interacting Sequential Circuits (AG, SD, ARN), pp. 213–219.
DAC-1990-GhoshDN90a #generative #logic #testing: Sequential Test Generation at the Register-Transfer and Logic Levels (AG, SD, ARN), pp. 580–586.
DAC-1989-Devadas #logic #multi #synthesis: Approaches to Multi-level Sequential Logic Synthesis (SD), pp. 270–276.
DAC-1989-Devadas89a #composition: General Decomposition of Sequential Machines: Relationships to State Assignment (SD), pp. 314–320.
DAC-1987-DevadasMN #abstraction #on the #verification: On the Verification of Sequential Machines at Differing Levels of Abstraction (SD, HKTM, ARN), pp. 271–276.
DAC-1987-MaDSW #algorithm #implementation #logic #parallel #verification: Logic Verification Algorithms and Their Parallel Implementation (HKTM, SD, ALSV, RW), pp. 283–290.
DAC-1986-BraunBDMMRS #multi #named: Chameleon: a new multi-layer channel router (DB, JLB, SD, HKTM, KM, FR, ALSV), pp. 495–502.
DAC-1986-DevadasN #array #named #synthesis: GENIE: a generalized array optimizer for VLSI synthesis (SD, ARN), pp. 631–637.