BibSLEIGH — Proceedings of the 24th Design Automation Conference

A. O'Neill, D. Thomas
Proceedings of the 24th Design Automation Conference
DAC, 1987.

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@proceedings{DAC-1987,
	acmid         = "37888",
	editor        = "A. O'Neill and D. Thomas",
	publisher     = "{IEEE Computer Society Press / ACM}",
	title         = "{Proceedings of the 24th Design Automation Conference}",
	year          = 1987,
}

Contents (128 items)

DAC-1987-WangHPZ #named: SSIM: A Software Levelized Compiled-Code Simulator (LTW, NEH, EHP, JJZ), pp. 2–8.
DAC-1987-BryantBBCS #named: COSMOS: A Compiled Simulator for MOS Circuits (REB, DLB, KSB, KC, TJS), pp. 9–16.
DAC-1987-TanTBVP #performance #self #simulation: A Fast Signature Simulation Tool for Built-In Self-Testing Circuits (SBT, KT, KB, PV, RP), pp. 17–25.
DAC-1987-FaroughiS #algorithm #array: An Improved Systematic Method for Constructing Systolic Arrays from Algorithms (NF, MAS), pp. 26–34.
DAC-1987-JainPP #design #pipes and filters #predict #trade-off: Predicting Area-Time Tradeoffs for Pipelined Design (RJ, ACP, NP), pp. 35–41.
DAC-1987-HarjaniRC #framework #knowledge-based #prototype #synthesis: A Prototype Framework for Knowledge-Based Analog Circuit Synthesis (RH, RAR, LRC), pp. 42–49.
DAC-1987-Chi #automation #clustering #standard: An Automatic Rectilinear Partitioning Procedure for Standard Cells (MCC), pp. 50–55.
DAC-1987-Grover #standard #using: Standard Cell Placement Using Simulated Sintering (LKG), pp. 56–59.
DAC-1987-KlingB #evolution #named #standard #using: ESP: A New Standard Cell Placement Package Using Simulated Evolution (RMK, PB), pp. 60–66.
DAC-1987-Masurkar #re-engineering #requirements: Requirements for a Practical Software Engineering Environment (VM), pp. 67–73.
DAC-1987-Rosenberg #perspective #re-engineering: The Making of VIVID: A Software Engineering Perspective (JBR), pp. 74–81.
DAC-1987-Elias #case study #compilation #generative #layout #re-engineering: A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator (NJE), pp. 82–88.
DAC-1987-VladimirescuWKBKDNJL #hardware #simulation: A Vector Hardware Accelerator with Circuit Simulation Emphasis (AV, DW, MK, ZB, AK, KD, KCN, NJ, SL), pp. 89–94.
DAC-1987-Smith #hardware #scalability: A Hardware Switch Level Simulator for Large MOS Circuits (MTS), pp. 95–100.
DAC-1987-AgrawalDEFJK #architecture #design #hardware: Architecture and Design of the MARS Hardware Accelerator (PA, WJD, AKE, WCF, HVJ, ASK), pp. 101–107.
DAC-1987-WebberS #simulation: Circuit Simulation on the Connection Machine (DMW, ALSV), pp. 108–113.
DAC-1987-Hedlund #automation #named: Aesop: A Tool for Automated Transistor Sizing (KSH), pp. 114–120.
DAC-1987-Cirit: Transistor Sizing in CMOS Circuits (MAC), pp. 121–124.
DAC-1987-HofmannK #logic #optimisation: Delay Optimization of Combinational Static CMOS Logic (MH, JKK), pp. 125–132.
DAC-1987-CanrightH #logic: Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic (REC, ARH), pp. 133–139.
DAC-1987-RoylePVNS #geometry: Geometrical Compaction in One Dimension for Channel Routing (JR, MP, HV, NN, JS), pp. 140–145.
DAC-1987-Polkl: A Three-Layer Gridless Channel Router with Compaction (DBP), pp. 146–151.
DAC-1987-Chen: Routing L-Shaped Channels in Nonslicing-Structure Placement (HHC), pp. 152–158.
DAC-1987-NaclerieMN: Via Minimization for Gridless Layouts (NJN, SM, KN), pp. 159–165.
DAC-1987-Trevillyan #logic #overview #synthesis: An Overview of Logic Synthesis Systems (LT), pp. 166–172.
DAC-1987-Maly #fault #modelling #testing: Realistic Fault Modeling for VLSI Testing (WM), pp. 173–180.
DAC-1987-SmithMB #simulation: Demand Driven Simulation: BACKSIM (SPS, MRM, BB), pp. 181–187.
DAC-1987-SmithSS #architecture #parallel #performance #simulation: Faster Architectural Simulation Through Parallelism (JWS, KSS, RJSI), pp. 189–194.
DAC-1987-PaulinK #automation #scheduling #synthesis: Force-Directed Scheduling in Automatic Data Path Synthesis (PGP, JPK), pp. 195–202.
DAC-1987-BrewerG #architecture #design #knowledge base: Knowledge Based Control in Micro-Architecture Design (FB, DG), pp. 203–209.
DAC-1987-KurdahiP #named: REAL: a program for REgister ALlocation (FJK, ACP), pp. 210–215.
DAC-1987-McGehee: A Practical Moat Router (RKM), pp. 216–222.
DAC-1987-Chowdhury #automation #design: An Automated Design of Minimum-Area IC Power/Ground Nets (SC), pp. 223–229.
DAC-1987-HealeyK #generative #logic #network: Abstract Routing of Logic Networks for Custom Module Generation (STH, WJK), pp. 230–236.
DAC-1987-SchultzB #fault #simulation: Accelerated Transition Fault Simulation (MHS, FB), pp. 237–243.
DAC-1987-RajsumanMJ #fault #modelling #on the: On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates (RR, YKM, APJ), pp. 244–250.
DAC-1987-ConcinaL #design: Integrating Design Information for IC Diagnosis (SEC, GSL), pp. 251–257.
DAC-1987-McDermottS #network #paradigm: Switch Directed Dynamic Causal Networks — a Paradigm for Electronic System Diagnosis (RMM, DS), pp. 258–264.
DAC-1987-Weise #functional #verification: Functional Verification of MOS Circuits (DW), pp. 265–270.
DAC-1987-DevadasMN #abstraction #on the #verification: On the Verification of Sequential Machines at Differing Levels of Abstraction (SD, HKTM, ARN), pp. 271–276.
DAC-1987-ChandrasekharPC #design #hardware #term rewriting #verification: Application of Term Rewriting Techniques to Hardware Design Verification (MSC, JPP, KWC), pp. 277–282.
DAC-1987-MaDSW #algorithm #implementation #logic #parallel #verification: Logic Verification Algorithms and Their Parallel Implementation (HKTM, SD, ALSV, RW), pp. 283–290.
DAC-1987-CarpenterH #constraints #generative #incremental: Generating Incremental VLSI Compaction Spacing Constraints (CWC, MH), pp. 291–297.
DAC-1987-XiongK #named #performance: Nutcracker: An Efficient and Intelligent Channel Spacer (XMX, ESK), pp. 298–304.
DAC-1987-NylandDR: Improving Virtual-Grid Compaction Through Grouping (LSN, SWD, CDR), pp. 305–310.
DAC-1987-LinN #named: KAHLUA: A Hierarchical Circuit Disassembler (BL, ARN), pp. 311–317.
DAC-1987-Preas #benchmark #layout #metric: Benchmarks for Cell-Based Layout Systems (BP), pp. 319–320.
DAC-1987-BhatejaK #design #named #validation: VALKYRIE: A Validation Subsystem of a Version Server for Computer-Aided Design Data (RB, RHK), pp. 321–327.
DAC-1987-RosenthalH #approach #knowledge-based #query: Querying Part Hierarchies: A Knowledge-Based Approach (AR, SH), pp. 328–334.
DAC-1987-HeilerDAOR #approach #data transformation #database #design #object-oriented #why: An Object-Oriented Approach to Data Management: Why Design Databases Need It (SH, UD, JAO, SRS), pp. 335–340.
DAC-1987-Keutzer #graph #named #optimisation: DAGON: Technology Binding and Local Optimization by DAG Matching (KK), pp. 341–347.
DAC-1987-BeekmanOI #array #generative #performance: Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation (JAB, RMO, MJI), pp. 357–362.
DAC-1987-FriedmanS #diagrams: Finding the Optimal Variable Ordering for Binary Decision Diagrams (SJF, KJS), pp. 358–356.
DAC-1987-ApteK #layout #standard: Strip Layout: A New Layout Methodology for Standard Circuit Modules (JA, GK), pp. 363–369.
DAC-1987-SchuckWGK #compilation #design #experience #implementation: The ALGIC Silicon Compiler System: Implementation, Design Experience and Results (JS, NW, MG, GK), pp. 370–375.
DAC-1987-DaiSK #layout #performance #representation: A Dynamic and Efficient Representation of Building-Block Layout (WWMD, MS, ESK), pp. 376–384.
DAC-1987-LiuSU #array #design #logic #named #programmable #scalability #self: BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays (CYL, KKS, SJU), pp. 385–391.
DAC-1987-Wunderlich #on the #random testing #testing: On Computing Optimized Input Probabilities for Random Tests (HJW), pp. 392–398.
DAC-1987-YuKL #adaptation #optimisation #testing #using: VLSI Circuit Testing Using an Adaptive Optimization Model (PSY, CMK, YHL), pp. 399–406.
DAC-1987-KrasniewskiP #low cost #self: Circular Self-Test Path: A Low-Cost BIST Technique (AK, SP), pp. 407–415.
DAC-1987-GranackiP #interface #named #natural language #specification: PHRAN-SPAN: A Natural Language Interface for System Specifications (JJGJ, ACP), pp. 416–422.
DAC-1987-LeeLP #editing #named #visual notation: TED: A Graphical Technology Description Editor (WL, GL, KP), pp. 423–428.
DAC-1987-Lee #hypermedia #quote: “?”: A Context-Sensitive Help System Based on Hypertext (WL), pp. 429–435.
DAC-1987-ChunCM #named: VISION: VHDL Induced Schematic Imaging on Net-Lists (RKC, KJC, LPM), pp. 436–442.
DAC-1987-JohannsenTM #compilation: An Intelligent Compiler Subsystem for a Silicon Compiler (DLJ, SKT, KM), pp. 443–450.
DAC-1987-Serlet #combinator #performance: Fast, Small, and Static Combinatorial CMOS Circuits (BS), pp. 451–458.
DAC-1987-Subrahmanyam #deduction #named: LCS — A Leaf Cell Synthesizer Employing Formal Deduction Techniques (PAS), pp. 459–465.
DAC-1987-ChenC #compilation #design #independence: A Design Rule Independent Cell Compiler (JSJC, DYC), pp. 466–471.
DAC-1987-Shahdad #interface: An Interface between VHDL and EDIF (MS), pp. 472–478.
DAC-1987-Parks #analysis #design #named #tutorial: Tutorial: Reading and Reviewing the Common Schema for Electrical Design and Analysis (CHP), pp. 479–483.
DAC-1987-Saunders #design: The IBM VHDL Design System (LFS), pp. 484–490.
DAC-1987-Hines: Where VHDL Fits Within the CAD Environment (JH), pp. 491–494.
DAC-1987-ChandraP #approach #generative: A Hierarchical Approach Test Vector Generation (SJC, JHP), pp. 495–501.
DAC-1987-KirklandM #algorithm: A Topological Search Algorithm for ATPG (TEK, MRM), pp. 502–508.
DAC-1987-LadjadjM #benchmark #metric: Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits (ML, JFM), pp. 509–515.
DAC-1987-OwensI #design #overview: An Overview of the Penn State Design System (RMO, MJI), pp. 516–522.
DAC-1987-SuzukiBKTS #automation #named: TRIP: An Automated Technology Mapping System (SS, TB, MK, KT, TS), pp. 523–529.
DAC-1987-OgiharaTM #design #named: ASTA: LSI Design Management System (TO, HT, SM), pp. 530–536.
DAC-1987-WongL #array #optimisation #synthesis: Array Optimization for VLSI Synthesis (DFW, CLL), pp. 537–543.
DAC-1987-MaiaszH #functional #layout #optimisation: Layout Optimization of CMOS Functional Cells (RLM, JPH), pp. 544–551.
DAC-1987-ChangCH #approach #automation #generative #layout #matrix #using: Automated Layout Generation Using Gate Matrix Approach (YCC, SCC, LHH), pp. 552–558.
DAC-1987-Waxman #automation #design #standard: The Design Automation Standards Environment (RW), pp. 559–561.
DAC-1987-OConnell #automation #design #integration #standard: Design Automation Standards Need Integration (LO), p. 562.
DAC-1987-Pachter #automation #design #standard: Design Automation Standards — Perspectives from a Down-the-Road End User (RJP), pp. 563–564.
DAC-1987-Brei #metalanguage #named #representation: Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation Mechanisms (MLB), p. 565.
DAC-1987-SuRT #named: HPEX: A Hierarchical Parasitic Circuit Extractor (SLS, VBR, TNT), pp. 566–569.
DAC-1987-StarkH #named #simulation: RED: Resistance Extraction for Digital Simulation (DS, MH), pp. 570–573.
DAC-1987-WuHHYY #behaviour: Function Search from Behavioral Description of a Digital System (JGW, WPCH, YHH, DYYY, HJY), pp. 574–579.
DAC-1987-Kingsley #compilation #implementation #state machine: The Implementation of a State Machine Compiler (CK), pp. 580–583.
DAC-1987-StablerB #comparison #simulation: Boolean Comparison by Simulation (EPS, HB), pp. 584–587.
DAC-1987-SouleB #abstraction #parallel #simulation #statistics: Statistics for Parallelism and Abstraction Level in Digital Simulation (LS, RB), pp. 588–591.
DAC-1987-LeungS #concept #design #framework #hardware: A Conceptual Framework for Designing ASIC Hardware (SSL, MAS), pp. 592–595.
DAC-1987-Bulterman #architecture #automation #design #named: CASE: An Integrated Design Environment for Algorithm-Driven Architectures (DCAB), pp. 596–599.
DAC-1987-GalivancheR #parallel: A Parallel PLA Minimization Program (RG, SMR), pp. 600–607.
DAC-1987-LursinsapG: Improving a PLA Area by Pull-Up Transistor Folding (CL, DG), pp. 608–614.
DAC-1987-NguyenPG #named #performance: PALMINI — Fast Boolean Minimizer for Personal Computers (LBN, MAP, NBG), pp. 615–621.
DAC-1987-Wey #array #design #logic #on the #programmable: On Yield Consideration for the Design of Redundant Programmable Logic Arrays (CLW), pp. 622–628.
DAC-1987-Kaplan #approach: Routing with a Scanning Window-8Ma Unified Approach (DK), pp. 629–632.
DAC-1987-Ng #design: A “gridless” Variable-Width Channel Router for Marco Cell Design (CHN), pp. 633–636.
DAC-1987-EnbodyD: General Purpose Router (RJE, HCD), pp. 637–640.
DAC-1987-HsuPK: A Path Selection Global Router (YCH, YP, WJK), pp. 641–644.
DAC-1987-ShahM: A New Compaction Scheme Based on Compression Ridges (PCS, HNM), pp. 645–648.
DAC-1987-BeckerHKMO #calculus #design: Hierarchical Design Based on a Calculus of Nets (BB, GH, RK, PM, HGO), pp. 649–653.
DAC-1987-KoukaS #data analysis #design: An Application of Exploratory Data Analysis Techniques to Floorplan Design (EFMK, GS), pp. 654–658.
DAC-1987-LueM #game studies #layout #named: PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement (WJL, LPM), pp. 659–665.
DAC-1987-CesearIT #named #synthesis: PAMS: An Expert System for Parameterized Module Synthesis (TC, EI, CT), pp. 666–671.
DAC-1987-LinG #layout #named: LES: A Layout Expert System (YLSL, DG), pp. 672–678.
DAC-1987-Steele #design: An Expert System Application in Semicustom VLSI Design (RLS), pp. 679–688.
DAC-1987-MazumderPF #algorithm #design #parallel #random #testing: Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories (PM, JHP, WKF), pp. 689–694.
DAC-1987-Krishnamurthy #approach #problem #programming: A Dynamic Programming Approach to the Test Point Insertion Problem (BK), pp. 695–705.
DAC-1987-PraizlerF: A Parts Selection Expert System to Increase Manufacturability (DP, GF), pp. 706–712.
DAC-1987-TouKFH #approach #automation #database #knowledge base #verification: Knowledge Based Approach for the Verification of CAD Database Generated by an Automated Schematic Capture System (JYT, WHK, KCF, CLH), pp. 713–720.
DAC-1987-Rosenberg87a #interactive: A New Interactive Supply/Demand Router with Rip-Up Capability for Printed Circuit Boards (ER), pp. 721–726.
DAC-1987-Dion #performance: Fast Printed Circuit Board Routing (JD), pp. 727–734.
DAC-1987-Forbes #heuristic: Heuristic Acceleration of Force-Directed Placement (RF), pp. 735–740.
DAC-1987-MorisonPTW #design #named: EASE: A Design Support Environment for the HDDL ELLA (JDM, NEP, TLT, EVW), pp. 741–749.
DAC-1987-DemersJFC #integration #named #object-oriented #tool support: CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools (LPD, PJ, SF, EC), pp. 750–756.
DAC-1987-GirczycL #design #mvc #named #smalltalk: STEM: An IC Design Environment Based on the Smalltalk Model-View-Controller Construct (EFG, TAL), pp. 757–763.
DAC-1987-GadientE #information management: Rational for and Organization of the Engineering Information System Program (AJG, JLE), pp. 764–769.
DAC-1987-MinaiWB #approach #evaluation #heuristic #predict: A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts (AAM, RDW, FWB), pp. 770–776.
DAC-1987-OdawaraHIYD #rule-based: A Rule-Based Placement System for Printed Wiring Boards (GO, TH, KI, TY, YD), pp. 777–785.
DAC-1987-WuWN #automation #design #representation #rule-based #verification: A Rule-Based Circuit Representation for Automated CMOS Design and Verification (CFEW, ASW, LMN), pp. 786–792.
DAC-1987-SpiersE #performance: A High Performance Routing Engine (TDS, DAE), pp. 793–799.
DAC-1987-WonSE #hardware: A Hardware Accelerator for Maze Routing (YW, SS, YMEZ), pp. 800–806.
DAC-1987-JonesB #algorithm #parallel #performance #standard: Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube (MJ, PB), pp. 807–813.
DAC-1987-OlukotunM #parallel: A Preliminary Investigation into Parallel Routing on a Hypercube Computer (KO, TNM), pp. 814–820.
DAC-1987-LathropHK #abstraction #functional #modelling #simulation: Functional Abstraction from Structure in VLSI Simulation Models (RHL, RJH, RSK), pp. 822–828.
DAC-1987-Koeppe #fault #layout: Optimal Layout to Avoid CMOS Stuck-Open Faults (SK), pp. 829–835.

A. O'Neill, D. ThomasProceedings of the 24th Design Automation ConferenceDAC, 1987.

Contents (128 items)

A. O'Neill, D. Thomas
Proceedings of the 24th Design Automation Conference
DAC, 1987.