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Travelled to:
1 × USA
Collaborated with:
S.Sahni
Talks about:
checker (1) systol (1) design (1) rule (1)

Person: Rajiv Kane

DBLP DBLP: Kane:Rajiv

Contributed to:

DAC 19841984

Wrote 1 papers:

DAC-1984-KaneS #design
A systolic design rule checker (RK, SS), pp. 243–250.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.