Patricia H. Lambert, Hillel Ofek, Lawrence A. O'Neill, Pat O. Pistilli, Paul Losleben, J. D. Nash, Dennis W. Shaklee, Bryan T. Preas, Harvey N. Lerman
Proceedings of the 21st Design Automation Conference
DAC, 1984.

@proceedings{DAC-1984,
	acmid         = "800033",
	address       = "Albuquerque, New Mexico, USA",
	editor        = "Patricia H. Lambert and Hillel Ofek and Lawrence A. O'Neill and Pat O. Pistilli and Paul Losleben and J. D. Nash and Dennis W. Shaklee and Bryan T. Preas and Harvey N. Lerman",
	isbn          = "0-8186-0542-1",
	publisher     = "{ACM/IEEE}",
	title         = "{Proceedings of the 21st Design Automation Conference}",
	year          = 1984,
}

Contents (123 items)

43 ×#design
19 ×#named
12 ×#layout
11 ×#algorithm
9 ×#automation
9 ×#verification
8 ×#logic
8 ×#testing
7 ×#multi
6 ×#hardware

DAC-1984-KawaiH #fault #simulation

An experimental MOS fault simulation program CSASIM (MK, JPH), pp. 2–9.

DAC-1984-ChenLNS #generative

The second generation motis mixed-mode simulator (CFC, CYL, HNN, PS), pp. 10–17.

DAC-1984-JainA #fault #named #simulation

STAFAN: An alternative to fault simulation (SKJ, VDA), pp. 18–23.

DAC-1984-DoshiSS #interactive #logic #multi

THEMIS logic simulator — a mix mode, multi-level, hierarchical, interactive digital circuit simulator (MHD, RBS, DMS), pp. 24–31.

DAC-1984-Dupenloup #array

A wire routing scheme for double-layer cell arrays (GD), pp. 32–37.

DAC-1984-Yoshimura #performance

An efficient channel router (TY), pp. 38–44.

DAC-1984-Clow #algorithm

A global routing algorithm for general cells (GWC), pp. 45–51.

DAC-1984-Ng #design

A symbolic-interconnect router for custom IC design (CHN), pp. 52–58.

DAC-1984-VeigaL #hardware #multi #named

HARPA: A hierarchical multi-level hardware description language (PV, ML), pp. 59–65.

DAC-1984-EvansBD #algorithm #design #named #synthesis

ADL: An algorithmic design language for integrated circuit synthesis (WHE, JCB, NHD), pp. 66–72.

DAC-1984-OdawaraST #functional

A symbolic functional description language (GO, JS, MT), pp. 73–80.

DAC-1984-SlutzOW

Block description language (BDL): A structural description language (ES, GO, JW), pp. 81–85.

DAC-1984-Gajski #compilation

Silicon compilers and expert systems for VLSI (DDG), pp. 86–87.

DAC-1984-ChuS #generative #independence #multi

A technology independent MOS multiplier generator (KcC, RS), pp. 90–97.

DAC-1984-PowellE #interpreter

The icewater language and interpreter (PADP, MIE), pp. 98–102.

DAC-1984-LursinsapG #compilation #constraints

Cell compilation with constraints (CL, DG), pp. 103–108.

DAC-1984-Ross #design #implementation #performance

Efficient implementation of experimental design systems (GDMR), p. 109.

DAC-1984-Hardwick #database #design #relational

Extending the relational database data model for design applications (MH), pp. 110–116.

DAC-1984-HollaarNCL #database #design #relational

The structure and operation of a relational database system in a cell-oriented integrated circuit design system (LAH, BEN, TMC, RAL), pp. 117–125.

DAC-1984-Kingsley

A hiererachical, error-tolerant compactor (CK), pp. 126–132.

DAC-1984-DunlopADJKW #layout #optimisation #using

Chip layout optimization using critical path weighting (AED, VDA, DND, MFJ, PK, MW), pp. 133–136.

DAC-1984-Mori #interactive #layout

Interactive compaction router for VLSI layout (HM), pp. 137–143.

DAC-1984-HorstmannS #design #logic programming #using

Computer aided design (CAD) using logic programming (PWH, EPS), pp. 144–151.

DAC-1984-OusterhoutHMST #layout #named

Magic: A VLSI layout system (JKO, GTH, RNM, WSS, GST), pp. 152–159.

DAC-1984-TaylorO #incremental

Magic’s incremental design-rule checker (GST, JKO), pp. 160–165.

DAC-1984-ScottO #interactive #named

Plowing: Interactive stretching and compaction in magic (WSS, JKO), pp. 166–172.

DAC-1984-HamachiO

A switchbox router with obstacle avoidance (GTH, JKO), pp. 173–179.

DAC-1984-AbadirR #case study #generative #testing

Test generation for LSI: A case study (MSA, HKR), pp. 180–195.

DAC-1984-KarpovskyM #approach #testing

An approach to the testing of microprocessors (MGK, RVM), pp. 196–202.

DAC-1984-DasguptaGRWW #clustering #design #testing

Chip partitioning aid: A design technique for partitionability and testability in VLSI (SD, MCG, RAR, RGW, TWW), pp. 203–208.

DAC-1984-Trischler #automation #design #generative #overview #perspective #testing

An integrated design for testability and automatic test pattern generation system: An overview (ET), pp. 209–215.

DAC-1984-Cavin #design

Introduction to the SRC design sciences program (RKCI), pp. 216–217.

DAC-1984-Smith #layout #tool support #what

Basic turorial layout tools — what really is there (RS), p. 219.

DAC-1984-HeidenG #design

Ergonomic studies in computer aided design (GHvdH, EG), pp. 220–227.

DAC-1984-KawamuraTH #functional #memory management #verification

Functional verification of memory circuits from mask artwork data (MK, HT, KH), pp. 228–234.

DAC-1984-ChapmanC #approach #case study #design #experience

The scan line approach to design rules checking: Computational experiences (PTC, KCJ), pp. 235–241.

DAC-1984-KaneS #design

A systolic design rule checker (RK, SS), pp. 243–250.

DAC-1984-Milne #hardware #verification

A model for hardware description and verification (GJM), pp. 251–257.

DAC-1984-AlaliDM #logic

A model for non interpreted structures of logical systems (RA, CD, JJM), pp. 258–264.

DAC-1984-Lieberherr #hardware #standard #towards

Towards a standard hardware description language (KJL), pp. 265–272.

DAC-1984-Parks #design

IGES as an interchange format for integrated circuit design (CHP), pp. 273–274.

DAC-1984-Jackson #design #multi

A designing system for multi-family housing (BJ), pp. 275–281.

DAC-1984-Wilkins #design #verification

Module design verification system (LW), pp. 282–287.

DAC-1984-Price

Studying the mouse for CAD systems (LAP), pp. 288–293.

DAC-1984-LotvinJG #layout #named

Amoeba: A symbolic VLSI layout system (ML, BJ, RG), pp. 294–300.

DAC-1984-KaoMS #design #named

ARIES: A workstation based, schematic driven system for circuit design (WHK, MHME, MLS), pp. 301–307.

DAC-1984-DussaultLT #design #synthesis

A high level synthesis tool for MOS chip design (JPD, CCL, MMT), pp. 308–314.

DAC-1984-TsengS #design #named

Emerald: A bus style designer (CJT, DPS), pp. 315–321.

DAC-1984-ShinshaKHAI #algorithm #logic #named #synthesis

Polaris: Polarity propagation algorithm for combinational logic synthesis (TS, TK, MH, KA, KI), pp. 322–328.

DAC-1984-ParkerKM #design #synthesis #verification

A general methodology for synthesis and verification of register-transfer designs (ACP, FJK, MJM), pp. 329–335.

DAC-1984-GlazierA #hardware #logic #named #simulation

Ultimate: A hardware logic simulation engine (MEG, APA), pp. 336–342.

DAC-1984-dAbreuCF #design #named

Oracle — a simulator for Bipolar and MOS IC design (MAd, KLC, CTF), pp. 343–349.

DAC-1984-DeutschN #implementation #multi #simulation

A multiprocessor implementation of relaxation-based electrical circuit simulation (JTD, ARN), pp. 350–357.

DAC-1984-EtiembleADB #algorithm #evaluation

Micro-computer oriented algorithms for delay evaluation of MOS gates (DE, VA, NHD, JCB), pp. 358–364.

DAC-1984-Foster #design

A unified CAD system for electronic design (JCF), pp. 365–369.

DAC-1984-ChangT #aspect-oriented #design

Engineering design aspects (HYC, RNT), pp. 370–373.

DAC-1984-Rosenthal #aspect-oriented #design #physics

Physical design and manufacturing information aspects aspects of the AT & T bell laboratories CAD system (CWR), pp. 374–383.

DAC-1984-ColtonSE #perspective

Users view (JC, FES, DHE), p. 384.

DAC-1984-Hinchliffe #array #automation #design #physics

Commercial gate array physical design automation packages (FHI), pp. 386–387.

DAC-1984-ChenK #design #layout #problem

The channel expansion problem in layout design (RRC, YK), pp. 388–391.

DAC-1984-Richard #standard

A standard cell initial placement strategy (BDR), pp. 392–398.

DAC-1984-Palczewski #algorithm #performance

Performance of algorithms for initial placement (MP), pp. 399–404.

DAC-1984-Roach

The rectangle placement language (JAR), pp. 405–411.

DAC-1984-SteinbergM #approach #knowledge base

A knowledge based approach to VLSI CAD the redesign system (LIS, TMM), pp. 412–418.

DAC-1984-Kelly #automation #design

The CRITTER system: Automated critiquing of digital circuit designs (VEK), pp. 419–425.

DAC-1984-LewandowskiL #algorithm #bound #branch

A branch and bound algorithm for optimal pla folding (JLL, CLL), pp. 426–433.

DAC-1984-MeyerAP #automaton #design

A VLSI FSM design system (MJM, PA, RGP), pp. 434–440.

DAC-1984-SabetySM #automation #generative #parallel

The semi-automatic generation of processing element control paths for highly parallel machines (TS, DES, BM), pp. 441–446.

DAC-1984-Freund #design #scalability #testing

Managing a large volume of design/manufacturing/test data in a chip and module factory (VJFJ), pp. 447–451.

DAC-1984-GuillaumeK #named #proximity

MINUPROX — an advanced proximity correction technique for the IBM EL-2 electron beam tool (WJG, AK), pp. 452–453.

DAC-1984-SchnurmannVP #automation #memory management #testing

An automated system for testing LSI memory chips (HDS, LJV, RMP), pp. 454–458.

DAC-1984-Nachtsheim #automation #design

The Intel design automation system (SN), pp. 459–465.

DAC-1984-SherhartVO #design

The engineering design environment (KS, MV, JO), pp. 466–472.

DAC-1984-ThamWW #design #functional #multi #simulation #verification

Functional design verification by multi-level simulation (KT, RW, DW), pp. 473–478.

DAC-1984-MarW #performance #verification

Performance verification of circuits (JM, YPW), pp. 479–483.

DAC-1984-Wagner #layout #verification

Hierarchical layout verification (TJW), pp. 484–489.

DAC-1984-BellonV #functional

Taking into account asynchronous signals in functional test of complex circuits (CB, RV), pp. 490–496.

DAC-1984-SaucierB #control flow #using

VLSI test expertise system using a control flow model (GS, CB), pp. 497–503.

DAC-1984-ReddyAJ #detection #fault #logic

A gate level model for CMOS combinational logic circuits with application to fault detection (SMR, VDA, SKJ), pp. 504–509.

DAC-1984-Lieberherr84a #random testing #testing

Parameterized random testing (KJL), pp. 510–516.

DAC-1984-SuL #functional #testing

Functional testing techniques for digital LSI/VLSI systems (SYHS, TL), pp. 517–528.

DAC-1984-GlasserH #optimisation

Delay and power optimization in VLSI circuits (LAG, LH), pp. 529–535.

DAC-1984-GeusRRW #analysis #named

IDA: Interconnect delay analysis for integrated circuits (AJdG, JBR, MR, GW), pp. 536–541.

DAC-1984-Ousterhout #modelling

Switch-level delay models for digital MOS VLSI (JKO), pp. 542–548.

DAC-1984-TakahashiKYEF #logic #network #simulation

An MOS digital network model on a modified thevenin equivalent for logic simulation (TT, SK, OY, KE, HF), pp. 549–555.

DAC-1984-Dewey #hardware

The VHSIC hardware description language (VHDL) program (AD), pp. 556–557.

DAC-1984-Lanfri #geometry #named

Phled45: An enhanced version of caesar supporting 45° geometries (ARL), pp. 558–564.

DAC-1984-OzakiWKIS #layout #named

MGX: An integrated symbolic layout system for VLSI (MO, MW, MK, MI, KS), pp. 572–579.

DAC-1984-AndersonP

UTMC’s LSI CAD system — highland (KA, RP), pp. 580–586.

DAC-1984-Marwedel #design #tool support

The mimola design system: Tools for the design of digital processors (PM), pp. 587–593.

DAC-1984-WardleWWMN #approach #declarative #design

A declarative design approach for combining macrocells by directed placement and constructive routing (CLW, CRW, CAW, JCM, BJN), pp. 594–601.

DAC-1984-Snyder #industrial

A model for university, industry and government cooperation (LS), pp. 602–603.

DAC-1984-Scott #design #named #process #tutorial

Tutorial — mechanical workstation software computer aided engineering in the mechanical design process (JS), p. 605.

DAC-1984-Haas

Computervision’s direction in workstation technology (GDH), pp. 606–609.

DAC-1984-LuellauHB #algorithm #independence

A technology independent block extraction algorithm (FL, TH, EB), pp. 610–615.

DAC-1984-McCormick #design #named

EXCL: A circuit extractor for IC designs (SPM), pp. 616–623.

DAC-1984-KorsI #graph #interactive

An interactive electrical graph extractor (JLK, MI), pp. 624–628.

DAC-1984-ZhangW #database #geometry

Some consideration on the data model of geometric data bases (JZ, RW), pp. 629–633.

DAC-1984-DixonSC #architecture #design

An architecture for application of artificial intelligence to design (JRD, MKS, PRC), pp. 634–640.

DAC-1984-WojcikKS #automation #design #reasoning #verification

A formal design verification system based on an automated reasoning system (ASW, JKJ, NCES), pp. 641–647.

DAC-1984-Banin #automation #design #hardware

Hardware accelerators in the design automation environment (RB), p. 648.

DAC-1984-Zingale #how

The semi-custom revolution: How to thrive or survive (AZ), pp. 649–650.

DAC-1984-MarkovFB #2d #optimisation

Optimization techniques for two-dimensional placement (LAM, JRF, JHB), pp. 652–654.

DAC-1984-KozminskiK #algorithm #graph

An algorithm for finding a rectangular dual of a planar graph for use in area planning for VLSI integrated circuits (KK, EK), pp. 655–656.

DAC-1984-TienTCCE #array #automation #layout #named

GALA — an automatic layout system for high density CMOS gate arrays (BNT, BST, JC, KSKC, SCE), pp. 657–662.

DAC-1984-LeinwandL #algorithm

An algorithm for building rectangular floor-plans (SML, YTL), pp. 663–664.

DAC-1984-RaoRZ

Spider, a chip planner for ISL technology (PR, RR, GZ), pp. 665–666.

DAC-1984-KozawaMT #algorithm #layout #logic #top-down

Combine and top down block placement algorithm for hierarchical logic VLSI layout (TK, CM, HT), pp. 667–669.

DAC-1984-Blanks #array #using

Initial placement of gate arrays using least-squares methods (JPB), pp. 670–671.

DAC-1984-HudsonWP #algorithm

Module positioning algorithms for rectilinear macrocell assemblies (JAH, JAW, RCP), pp. 672–675.

DAC-1984-RajPG #synthesis

Microprocessor synthesis (VKR, BMP, DDG), pp. 676–678.

DAC-1984-PerskyT #multi

Topological routing of multi-bit data buses (GP, LVT), pp. 679–682.

DAC-1984-Crawford #design

An electronic design interchange format (JDC), pp. 683–685.

DAC-1984-KrieteN #design #metaprogramming #parametricity

A VLSI design methodology based on parametric macro cells (RAK, RKN), pp. 686–688.

DAC-1984-MartinezN #compilation

Methodology for compiler generated silicon structures (AM, SN), pp. 689–691.

DAC-1984-KatzW #design #transaction

Design transaction management (RHK, SW), pp. 692–693.

DAC-1984-AshokMR #design #problem #process

Uniform support for information handling and problem solving required by the VLSI design process (VA, WLM, JR), pp. 694–696.

DAC-1984-Trimberger #assembly #named #visual notation

VTIcompose — a powerful graphical chip assembly tool (ST), pp. 697–698.

DAC-1984-Biswas

Computer aided minimization procedure for boolean functions (NNB), pp. 699–702.

DAC-1984-WieclawskiP #compilation #layout #network #optimisation

Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler (AW, MAP), pp. 703–704.

DAC-1984-JhonK #analysis #concurrent #data flow #design

Deadlock analysis in the design of data-flow circuits (CSJ, RMK), pp. 705–707.

DAC-1984-Marvik #layout #verification

A method for IC layout verification (OAM), pp. 708–709.

DAC-1984-SastryP #logic #on the #slicing

On the relation between wire length distributions and placement of logic on master slice ICs (SS, ACP), pp. 710–711.