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Travelled to:
1 × Portugal
Collaborated with:
D.Cho G.Uh Y.Paek
Talks about:
preprocess (1) processor (1) strategi (1) schedul (1) signal (1) modulo (1) effect (1) multi (1) digit (1) issu (1)

Person: Ravi Ayyagari

DBLP DBLP: Ayyagari:Ravi

Contributed to:

CC 20072007

Wrote 1 papers:

CC-2007-ChoAUP #effectiveness #multi #preprocessor #scheduling
Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors (DC, RA, GRU, YP), pp. 16–31.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.