BibSLEIGH — Yunheung

Travelled to:

1 × Portugal
1 × Sweden
1 × United Kingdom
2 × Canada
2 × France
3 × Germany
5 × USA

Collaborated with:

A.Shrivastava S.Park J.Lee J.Lee D.Cho M.Ahn I.Heo Y.Lee D.B.Whalley Y.Kim N.Dutt J.Lee E.Earlie J.Cho J.Hoeflinger D.A.Padua J.W.Yoon J.Lee R.Ayyagari G.Uh H.Moon A.Sohn J.Ku Y.Kodama Y.Yamaguchi S.Pasricha I.Issenin S.Ko Y.Kim M.Kiemb K.Choi A.Nicolau N.D.Dutt A.Nicolau J.Jung P.A.Kulkarni W.Zhao H.Moon K.Cho J.W.Davidson M.W.Bailey K.Gallivan

Talks about:

architectur (4) processor (4) regist (3) memori (3) optim (3) embed (3) base (3) reconfigur (2) heterogen (2) algorithm (2)

Person: Yunheung Paek

DBLP: Paek:Yunheung

Facilitated 1 volumes:

Contributed to:

2015

2014

2011

2010

2008

2007

2006

2003

2002

1999

1998

Wrote 16 papers:

DAC-2015-LeeHLP #data flow #debugging #information management #interface #performance: Efficient dynamic information flow tracking on a processor with core debug interface (JL, IH, YL, YP), p. 6.
DATE-2015-LeeLMHP #monitoring #named #security: Extrax: security extension to extract cache resident information for snoop-based external monitors (JL, YL, HM, IH, YP), pp. 151–156.
LCTES-2014-LeeLLP #architecture #performance: Improving performance of loops on DIAM-based VLIW architectures (JL, JL, JL, YP), pp. 135–144.
DATE-2011-YoonLJPKPC #configuration management #embedded #incremental #named: I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics (JWY, JL, JJ, SP, YK, YP, DC), pp. 1346–1351.
LCTES-2010-KimLSP #memory management #multi: Operation and data mapping for CGRAs with multi-bank memory (YK, JL, AS, YP), pp. 17–26.
DATE-2008-ParkSP #embedded #execution #using: Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors (SP, AS, YP), pp. 1190–1195.
LCTES-2008-ChoPIDPK #array #compilation #data access #layout #optimisation: Compiler driven data layout optimization for regular/irregular array access patterns (DC, SP, II, ND, YP, SK), pp. 41–50.
CC-2007-ChoAUP #effectiveness #multi #preprocessor #scheduling: Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors (DC, RA, GRU, YP), pp. 16–31.
LCTES-2007-AhnLP #architecture: Optimistic coalescing for heterogeneous register architectures (MA, JL, YP), pp. 93–102.
DATE-2006-AhnYPKKC #algorithm #architecture #configuration management: A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures (MA, JWY, YP, YK, MK, KC), pp. 363–368.
DATE-2006-ParkESNDP #automation #embedded #generative #performance: Automatic generation of operation tables for fast exploration of bypasses in embedded processors (SP, EE, AS, AN, ND, YP), pp. 1197–1202.
LCTES-2006-ParkSDNPE #reduction #scheduling: Bypass aware instruction scheduling for register file power reduction (SP, AS, NDD, AN, YP, EE), pp. 173–181.
LCTES-2003-KulkarniZMCWDBPG #effectiveness #optimisation #sequence: Finding effective optimization phase sequences (PAK, WZ, HM, KC, DBW, JWD, MWB, YP, KG), pp. 12–23.
LCTES-SCOPES-2002-ChoPW #algorithm #architecture #graph #memory management #performance: Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms (JC, YP, DBW), pp. 130–138.
HPCA-1999-SohnPKKY #communication #parallel #thread: Communication Studies of Single-Threaded and Multithreaded Distributed-Memory Multiprocessors (AS, YP, JYK, YK, YY), pp. 310–314.
PLDI-1998-PaekHP #array #compilation #data access #optimisation: Simplification of Array Access Patterns for Compiler Optimizations (YP, JH, DAP), pp. 60–71.