Travelled to:1 × Canada
1 × France
1 × Germany
1 × Portugal
3 × USA
Collaborated with:D.B.Whalley P.Gavin M.Själander Y.Wang S.Jinturkar C.Burns V.Cao M.Yang D.Cho R.Ayyagari Y.Paek R.Baird I.Finlayson B.Davis G.S.Tyson
Talks about:effect (3) processor (2) overhead (2) pipelin (2) exploit (2) static (2) improv (2) effici (2) buffer (2) branch (2)
Person: Gang-Ryung Uh
DBLP: Uh:Gang=Ryung
Contributed to:
20152013
200720001999
1998
1997Wrote 7 papers:
- LCTES-2015-BairdGSWU #architecture #optimisation #pipes and filters
- Optimizing Transfers of Control in the Static Pipeline Architecture (RB, PG, MS, DBW, GRU), p. 10.
- LCTES-2013-FinlaysonDGUWST #performance #pipes and filters
- Improving processor efficiency by statically pipelining instructions (IF, BD, PG, GRU, DBW, MS, GST), pp. 33–44.
- CC-2007-ChoAUP #effectiveness #multi #preprocessor #scheduling
- Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors (DC, RA, GRU, YP), pp. 16–31.
- CC-2000-UhWWJBC #effectiveness
- Techniques for Effectively Exploiting a Zero Overhead Loop Buffer (GRU, YW, DBW, SJ, CB, VC), pp. 157–172.
- LCTES-1999-UhWWJBC #effectiveness
- Effective Exploitation of a Zero Overhead Loop Buffer (GRU, YW, DBW, SJ, CB, VC), pp. 10–19.
- PLDI-1998-YangUW #branch #order #performance
- Improving Performance by Branch Reordering (MY, GRU, DBW), pp. 130–141.
- SAS-1997-UhW #branch #performance
- Coalescing Conditional Branches into Efficient Indirect Jumps (GRU, DBW), pp. 315–329.