Collaborated with:S.K.Rajamani S.A.Seshia M.Costa A.Lal N.P.Lopes K.Vaswani
Talks about:methodolog (1) verifi (1) region (1) oblivi (1) design (1) comput (1) compil (1) access (1) verif (1) secur (1)
Person: Rohit Sinha 0001
DBLP: 0001:Rohit_Sinha
Contributed to:
2017
2016Wrote 2 papers:
- ESEC-FSE-2017-0001RS #compilation #verification
- A compiler and verifier for page access oblivious computation (RS0, SKR, SAS), pp. 649–660.
- PLDI-2016-0001CLLRSV #design #verification
- A design and verification methodology for secure isolated regions (RS0, MC, AL, NPL, SKR, SAS, KV), pp. 665–681.