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Travelled to:
1 × France
Collaborated with:
N.Menezes C.Oh L.T.Pillage M.R.Mercer
Talks about:
circuit (2) statist (1) predict (1) perform (1) analysi (1) level (1) time (1) use (1)

Person: Ronn B. Brashear

DBLP DBLP: Brashear:Ronn_B=

Contributed to:

EDAC-ETC-EUROASIC 19941994

Wrote 1 papers:

EDAC-1994-BrashearMOPM #analysis #performance #predict #statistics #using
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis (RBB, NM, CO, LTP, MRM), pp. 332–337.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.