Robert Werner
Proceedings of the European Conference on Design Automation (EDAC), European Test Conference (ETC) and the European Event in ASIC Design (EUROASIC)
EDAC-ETC-EUROASIC, 1994.

@proceedings{EDAC-1994,
	address       = "Paris, France",
	editor        = "Robert Werner",
	isbn          = "0-8186-5410-4",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the European Conference on Design Automation (EDAC), European Test Conference (ETC) and the European Event in ASIC Design (EUROASIC)}",
	year          = 1994,
}

Contents (125 items)

20 ×#fault
17 ×#testing
16 ×#design
16 ×#synthesis
12 ×#optimisation
12 ×#performance
8 ×#generative
8 ×#modelling
8 ×#using
7 ×#algorithm

EDAC-1994-AlexiouSK #composition #design #implementation #sorting

Design and Implementation of a High-Performance, Modular, Sorting Engine (GA, DS, NK), pp. 2–8.

EDAC-1994-GreinerLWW #complexity #design #library

Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library (AG, LL, FW, LW), pp. 9–13.

EDAC-1994-MichelLSDC #dependence

Taking Advantage of ASICs to Improve Dependability with Very Low Overheads (TM, RL, GS, RD, PC), pp. 14–18.

EDAC-1994-FranssenNSCM #control flow #optimisation #performance #simulation

Control flow optimization for fast system simulation and storage minimization (FHMF, LN, HS, FC, HDM), pp. 20–24.

EDAC-1994-HuangR #behaviour #performance #throughput #using

Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations (SHH, JMR), pp. 25–30.

EDAC-1994-LiemMP #code generation

Instruction-Set Matching and Selection for DSP and ASIP Code Generation (CL, TCM, PGP), pp. 31–37.

EDAC-1994-RudnickHSP #algorithm #generative #search-based #testing

Application of Simple Genetic Algorithms to Sequential Circuit Test Generation (EMR, JGH, DGS, JHP), pp. 40–45.

EDAC-1994-GaiMR #fault #named #performance

TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits (SG, PLM, MSR), pp. 46–50.

EDAC-1994-FummiSS #approach #fault #functional #generative #testing

A Functional Approach to Delay Faults Test Generation for Sequential Circuits (FF, DS, MS), pp. 51–57.

EDAC-1994-NguyenTDTV #cpu #logic #synthesis #verification

Logic Synthesis and Verification of the CPU and Caches of a Mainframe System (HNN, JPT, LD, MT, PV), pp. 60–64.

EDAC-1994-CalvoPM

ICM2 IC: a new ATM switching element for 2.48 Gb/s communications (FC, PP, PM), pp. 65–69.

EDAC-1994-DongenR #array #design

Advanced Analog Circuit Design on a Digital Sea-of-Gates Array (RvD, VR), pp. 70–74.

EDAC-1994-GevaertVNS

Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front End (DG, JV, JN, JS), pp. 75–79.

EDAC-1994-AjuhaM #reduction

Delay Reduction by Segment Substitution (HA, PRM), pp. 82–86.

EDAC-1994-RohfleischB #logic #optimisation

Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping (BR, FB), pp. 87–93.

EDAC-1994-GhatrajuAM #fixpoint #synthesis

High-Level Synthesis of Digital Circuits by Finding Fixpoints (LG, MHAEB, CM), pp. 94–98.

EDAC-1994-BrasenS #clustering

FPGA Partitioning for Critical Paths (DRB, GS), pp. 99–103.

EDAC-1994-LinGB #generative #low cost #novel

A Low Cost BIST Methodology and Associated Novel Test Pattern Generator (SPL, SKG, MAB), pp. 106–112.

EDAC-1994-Stroele #analysis

Signature Analysis for Sequential Circuits with Reset (APS), pp. 113–118.

EDAC-1994-HarrisO #concurrent #fine-grained #scheduling

Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST (IGH, AO), pp. 119–123.

EDAC-1994-IllmanT #architecture

A Fragmented Register Architecture and Test Advisor for BIST (RI, DJT), pp. 124–129.

EDAC-1994-ChenYF #debugging #design #identification #model checking

Bug Identification of a Real Chip Design by Symbolic Model Checking (BC, MY, MF), pp. 132–136.

EDAC-1994-ChoHMPS #algorithm #approximate #automaton #composition #traversal

A State Space Decomposition Algorithm for Approximate FSM Traversal (HC, GDH, EM, MP, FS), pp. 137–141.

EDAC-1994-HelbigK

An OBDD-Representation of Statecharts (JH, PK), pp. 142–149.

EDAC-1994-ZemvaBKZ #fault

A Functionality Fault Model: Feasibility and Applications (AZ, FB, KK, BZ), pp. 152–158.

EDAC-1994-FavalliDOR #fault #modelling

Modeling of Broken Connections Faults in CMOS ICs (MF, MD, PO, BR), pp. 159–164.

EDAC-1994-ChessL #fault #generative

Generating Test Patterns for Bridge Faults in CMOS ICs (BC, TL), pp. 165–170.

EDAC-1994-HahnKB #approach #fault

A Hierarchical Approach to Fault Collapsing (RH, RK, BB), pp. 171–176.

EDAC-1994-LinKL #approach #synthesis

Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach (KJL, JWK, CSL), pp. 178–183.

EDAC-1994-WatanabeB #automaton #nondeterminism #pseudo

State Minimization of Pseudo Non-Deterministic FSM’s (YW, RKB), pp. 184–191.

EDAC-1994-Damiani #finite #nondeterminism #state machine

Nondeterministic finite-state machines and sequential don’t cares (MD), pp. 192–198.

EDAC-1994-BernGMS

Boolean Manipulation with Free BDD’s. First Experimental Results (JB, JG, CM, AS), pp. 200–207.

EDAC-1994-LangevinC #representation

An Extended OBDD Representation for Extended FSMs (ML, EC), pp. 208–213.

EDAC-1994-HachtelMPS #algorithm #finite #state machine

Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine (GDH, EM, AP, FS), pp. 214–218.

EDAC-1994-HaberlK #interface #maintenance #standard

Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface (OFH, TK), pp. 220–225.

EDAC-1994-Su #bound #random testing #testing

Random Testing of Interconnects in A Boundary Scan Environment (CS), pp. 226–231.

EDAC-1994-KarkkainenTW #bound #monitoring #power management #testing

Boundary Scan Testing Combined with Power Supply Current Monitoring (MK, KT, MW), pp. 232–235.

EDAC-1994-SarmientoE #implementation

Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide Technology (RS, KE), pp. 238–244.

EDAC-1994-CoulombP #fourier #pipes and filters

PLFP256 A Pipelined Fourier Processor (PC, FP), pp. 245–249.

EDAC-1994-VacherBGRS #fourier #implementation #parallel #performance

A VLSI Implementation of Parallel Fast Fourier Transform (AV, MB, AG, TR, AS), pp. 250–255.

EDAC-1994-Saucier #design #network #recognition

Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network (DJ, GS), pp. 256–260.

EDAC-1994-RamachandranGC #algorithm #array #clustering

An Algorithm for Array Variable Clustering (LR, DG, VC), pp. 262–266.

EDAC-1994-SrivastavaP #latency #linear #optimisation

Transforming Linear Systems for Joint Latency and Throughout Optimization (MBS, MP), pp. 267–271.

EDAC-1994-BhatiaJ #behaviour #named #overview #synthesis #testing

Genesis: A Behavioral Synthesis System for Hierarchical Testability (SB, NKJ), pp. 272–276.

EDAC-1994-WuTWL #behaviour #synthesis

A Synthesis Method for Mixed Synchronous / Asynchronous Behavior (TYW, TCT, ACHW, YLL), pp. 277–281.

EDAC-1994-VuksicF #approach #fault #testing

A New BIST Approach for Delay Fault Testing (AV, KF), pp. 284–288.

EDAC-1994-ChenG #generative #testing

BIST Test Pattern Generators for Stuck-Open and Delay Testing (CAC, SKG), pp. 289–296.

EDAC-1994-KeM #synthesis

Synthesis of Delay-Verifiable Two-Level Circuits (WK, PRM), pp. 297–301.

EDAC-1994-Wang #synthesis #testing

Synthesis of Sequential Machines with Reduced Testing Cost (SJW), pp. 302–306.

EDAC-1994-RamachandranK #synthesis

Incorporating the Controller Effects During Register Transfer Level Synthesis (CR, FJK), pp. 308–313.

EDAC-1994-HolmesG #algorithm #behaviour #generative

An Algorithm for Generation of Behavioral Shape Functions (NDH, DG), pp. 314–318.

EDAC-1994-DalkilicP #bound #scheduling #using

Optimal Operation Scheduling Using Resource Lower Bound Estimations (MED, VP), pp. 319–324.

EDAC-1994-GrantML #generative #hardware #optimisation

Optimization of Address Generator Hardware (DMG, JLvM, PERL), pp. 325–329.

EDAC-1994-BrashearMOPM #analysis #performance #predict #statistics #using

Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis (RBB, NM, CO, LTP, MRM), pp. 332–337.

EDAC-1994-SivaramanS #analysis #parametricity #towards

Towards Incorporating Device Parameter Variations in Timing Analysis (MS, AJS), pp. 338–342.

EDAC-1994-FrosslK #simulation

A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation (JF, TK), pp. 343–348.

EDAC-1994-SafiniaLS #analysis #functional #modelling

Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling (CS, RL, GS), pp. 349–353.

EDAC-1994-Rodriguez-MontanesF #analysis #fault #testing

Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability (RRM, JF), pp. 356–360.

EDAC-1994-Sachdev #logic #testing

Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing (MS), pp. 361–365.

EDAC-1994-IsernF #fault

Test of Bridging Faults in Scan-based Sequential Circuits (EI, JF), pp. 366–370.

EDAC-1994-McGowenF #case study #detection

A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT (RM, FJF), pp. 371–375.

EDAC-1994-VanbekbergenYLM #graph #interface #specification

A Generalized Signal Transition Graph Model for Specification of Complex Interfaces (PV, CYC, BL, HDM), pp. 378–384.

EDAC-1994-KorfS #interface #specification #synthesis

Interface Controller Synthesis from Requirement Specifications (FK, RS), pp. 385–394.

EDAC-1994-NarayanG #interface #synthesis

Synthesis of System-Level Bus Interfaces (SN, DG), pp. 395–399.

EDAC-1994-EsbensenM #algorithm #graph #problem #search-based

A Genetic Algorithm for the Steiner Problem in a Graph (HE, PM), pp. 402–406.

EDAC-1994-HuijbregtsEJ #design #on the

On Design Rule Correct Maze Routing (EPH, JTJvE, JAGJ), pp. 407–411.

EDAC-1994-WuM #2d #array #performance #programmable

An Efficient Router for 2-D Field Programmable Gate Arrays (YLW, MMS), pp. 412–416.

EDAC-1994-AkitaA #logic #power management #probability

A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability (JA, KA), pp. 420–424.

EDAC-1994-LinCHH #design

Cell Height Driven Transistor Sizing in a Cell Based Module Design (HRL, CLC, YCH, TH), pp. 425–429.

EDAC-1994-McCoyR

Non-Tree Routing (BAM, GR), pp. 430–434.

EDAC-1994-SousaGTW #fault #modelling

Fault Modeling and Defect Level Projections in Digital ICs (JTdS, FMG, JPT, TWW), pp. 436–442.

EDAC-1994-XueDJ #analysis #fault #float #probability

Probability Analysis for CMOS Floating Gate Faults (HX, CD, JAGJ), pp. 443–448.

EDAC-1994-JamoussiK #approach #evaluation #named #testing

M-Testability: An Approach for Data-Path Testability Evaluation (MJ, BK), pp. 449–455.

EDAC-1994-GajskiVN #refinement

A System-Design Methodology: Executable-Specification Refinement (DG, FV, SN), pp. 458–463.

EDAC-1994-IsmailOJ #clustering #interactive

Interactive System-level Partitioning with PARTIF (TBI, KO, AAJ), pp. 464–468.

EDAC-1994-EdwardsF #development #embedded #hardware

A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems (ME, JF), pp. 469–473.

EDAC-1994-NaganumaOH #algorithm #debugging #design #using #validation

High-Level Design Validation Using Algorithmic Debugging (JN, TO, TH), pp. 474–480.

EDAC-1994-RouzeyreDS #component #scheduling #synthesis

Component Selection, Scheduling and Control Schemes for High Level Synthesis (BR, DD, GS), pp. 482–489.

EDAC-1994-DepuydtGGM #graph #optimisation #pipes and filters #scheduling

Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization (FD, WG, GG, HDM), pp. 490–494.

EDAC-1994-YangMD #automaton #constraints #scheduling

Scheduling with Environmental Constraints based on Automata Representations (JCYY, GDM, MD), pp. 495–501.

EDAC-1994-SchoofsGM #architecture #design #multi #optimisation

Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures (KS, GG, HDM), pp. 502–506.

EDAC-1994-LinCL #fault #named #performance

TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator (MCL, JEC, CLL), pp. 508–512.

EDAC-1994-WittmannH #identification #optimisation #performance #testing

Efficient Path Identification for Delay Testing — Time and Space Optimization (HCW, MH), pp. 513–517.

EDAC-1994-DumasGLP #effectiveness #fault

Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis (DD, PG, CL, SP), pp. 518–523.

EDAC-1994-KunzmannB #fault

Gate-Delay Fault Test with Conventional Scan-Design (AK, FB), pp. 524–528.

EDAC-1994-DonnaySGSKL #automation #design

A Methodology for Analog Design Automation in Mixed-Signal ASICs (SD, KS, GGEG, WMCS, WK, DL), pp. 530–534.

EDAC-1994-MoserNAAP #approach #behaviour #modelling #visual notation

A Graphical Approach to Analogue Behavioural Modelling (VM, PN, HPA, LA, FP), pp. 535–539.

EDAC-1994-ByrneMLD #optimisation #overview #using

An Overview of Analogue Optimisation Using “AD-OPT” (EB, OM, DL, BD), pp. 540–545.

EDAC-1994-IkedaA

A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs (MI, KA), pp. 546–550.

EDAC-1994-LiW #automaton #fault #logic #simulation

Logic and Fault Simulation by Cellular Automata (YLL, CWW), pp. 552–556.

EDAC-1994-MichaelsS #modelling #simulation

Variable Accuracy Device Modeling for Event-Driven Circuit Simulation (KWM, AJS), pp. 557–561.

EDAC-1994-WangFF

An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits (JHW, JTF, WSF), pp. 562–566.

EDAC-1994-WangD #approximate #linear #optimisation #performance #using

An Efficient Yield Optimization Method Using A Two Step Linear Approximation of Circuit Performance (ZW, SWD), pp. 567–571.

EDAC-1994-NicolaidisB #array #implementation #multi #performance #self

Efficient Implementations of Self-Checking Multiply and Divide Arrays (MN, HB), pp. 574–579.

EDAC-1994-HellebrandW #self #synthesis

Synthesis of Self-Testable Controllers (SH, HJW), pp. 580–585.

EDAC-1994-KimCL #refinement #synthesis #testing

A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability (TK, KSC, CLL), pp. 586–590.

EDAC-1994-FlottesHR #automation #specification #synthesis

Automatic Synthesis of BISTed Data Paths From High Level Specification (MLF, DH, BR), pp. 591–598.

EDAC-1994-StraubeWS #design #named

HANDICAP — A System for Design Consulting (MS, WW, GS), pp. 600–604.

EDAC-1994-BartelsKSS #reliability #requirements #testing

Flow Management Requirements of a Test Harness for Testing the Reliability of an Electronic CAD System (GB, PK, KS, MS), pp. 605–609.

EDAC-1994-ParikhSBSG #automation #design #distributed #fault #framework

Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework (SP, MLB, JS, GR), pp. 610–617.

EDAC-1994-ChangCM #multi

Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions (SCC, DIC, MMS), pp. 620–624.

EDAC-1994-BaharCHMS #analysis #using

Timing Analysis of Combinational Circuits using ADD’s (RIB, HC, GDH, EM, FS), pp. 625–629.

EDAC-1994-WurthW #logic #multi #optimisation #performance

Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization (BW, NW), pp. 630–634.

EDAC-1994-CamuratiCPBS #design #modelling #verification

System-Level Modeling and Verification: a Comprehensive Design Methodology (PC, FC, PP, CB, BS), pp. 636–640.

EDAC-1994-BreuerFK #semantics

Clean formal semantics for VHDL (PTB, LSF, CDK), pp. 641–647.

EDAC-1994-SchneiderKK #verification

Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path (KS, TK, RK), pp. 648–652.

EDAC-1994-Vitsyn #process #standard

The Russian EDA Standards Activities (NMV), p. 654.

EDAC-1994-JohanssonVG #performance

“Underground Capacitors” Very Efficient Decoupling for High Performance UHF Signal Processing ICs (TJ, LRV, JMG), p. 655.

EDAC-1994-RobertGMT #classification #design #geometry #realtime

Design of a Real Time Geometric Classifier (MR, PG, JM, ST), p. 656.

EDAC-1994-BalboniCFS #architecture #array #behaviour

From Behavioral Description to Systolic Array Based Architectures (AB, CC, FF, DS), p. 657.

EDAC-1994-AbderrahmanKS #estimation

Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits (AA, BK, YS), p. 658.

EDAC-1994-AhmadM #automation #layout #named #reasoning

AREAL: Automated Reasoning Expert for Analogue Layout (HHA, RJM), p. 659.

EDAC-1994-DufourN #design #independence #process

An Optimizable Model for Process Independent Symbolic Design (JCD, JFN), p. 660.

EDAC-1994-WuLCL #clustering #distributed #fault #simulation

Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning (WCW, CLL, JEC, WYL), p. 661.

EDAC-1994-VermeirenSE #fault #simulation

A Suggestion for Accelerating the Analog Fault Simulation (WV, BS, GE), p. 662.

EDAC-1994-Koudakou #component #implementation #optimisation #statistics

Software Implementation and Statistical Optimization of Some Electronic Component’s Lifetime (KCK), p. 663.

EDAC-1994-BoniCFMO #fault #modelling #physics

Physical Modeling of Linearity Errors for the Diagnosis of High Resolution R-2R D/A Converters (AB, GC, GF, SM, MO), p. 664.

EDAC-1994-AhmedCC #approach #fault #modelling #optimisation #using

A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation (SA, PYKC, PC), p. 665.

EDAC-1994-AGZS #functional #testing

Functional Tests for Ring-Address SRAM-type FIFOs (AJvdG, YZ, IS), p. 666.

EDAC-1994-BeckerD #diagrams #functional #testing

Testability of Circuits Derived from Functional Decision Diagrams (BB, RD), p. 667.

EDAC-1994-HirechFGR #design #simulation #testing

A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking (MH, OF, AG, EHR), p. 668.

EDAC-1994-BurgunDGPS #complexity #logic #multi #synthesis

Multilevel Logic Synthesis of Very High Complexity Circuits (LB, ND, AG, EP, CS), p. 669.

EDAC-1994-BanerjeeRCP #graph transformation

Signal Transition Graph Transformations for Initializability (SB, RKR, STC, DKP), p. 670.

EDAC-1994-DhodhiAC #multi #synthesis

Synthesis of Application-Specific Multiprocessor Systems (MKD, IA, CYRC), p. 671.

EDAC-1994-ZepterG #data flow #generative

Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level Configurations (PZ, TG), p. 672.