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Travelled to:
1 × France
9 × USA
Collaborated with:
L.T.Pillage C.S.Amin S.Pullela C.V.Kashyap F.N.Najm C.Chen F.Dartu K.Killpack L.T.Pileggi J.Qian E.Chiprout R.B.Brashear C.Oh M.R.Mercer S.M.Burns M.Ketkar K.A.Bowman J.Tschanz V.De U.Choudhury N.Hakim Y.I.Ismail
Talks about:
time (5) statist (4) circuit (4) analysi (4) model (4) use (3) interconnect (2) optim (2) level (2) delay (2)

Person: Noel Menezes

DBLP DBLP: Menezes:Noel

Contributed to:

DAC 20082008
DAC 20072007
DAC 20062006
DAC 20052005
DAC 20042004
DAC 19991999
DAC 19951995
DAC 19941994
DAC 19931993

Wrote 10 papers:

DAC-2008-MenezesKA #grid #power management #verification
A “true” electrical cell model for timing, noise, and power grid verification (NM, CVK, CSA), pp. 462–467.
DAC-2007-BurnsKMBTD #analysis #comparative #design #statistics
Comparative Analysis of Conventional and Statistical Design Techniques (SMB, MK, NM, KAB, JT, VD), pp. 238–243.
DAC-2006-AminKMKC #library #multi
A multi-port current source model for multiple-input switching effects in CMOS library cells (CSA, CVK, NM, KK, EC), pp. 247–252.
DAC-2005-AminMKDCHI #analysis #how #question #statistics
Statistical static timing analysis: how simple can we get? (CSA, NM, KK, FD, UC, NH, YII), pp. 652–657.
DAC-2004-NajmM #analysis #statistics
Statistical timing analysis based on a timing yield model (FNN, NM), pp. 460–465.
DAC-1999-ChenM #using
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching (CPC, NM), pp. 502–506.
DAC-1995-MenezesPP #optimisation
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (NM, SP, LTP), pp. 690–695.
DAC-1994-DartuMQP #performance
A Gate-Delay Model for high-Speed CMOS Circuits (FD, NM, JQ, LTP), pp. 576–580.
EDAC-1994-BrashearMOPM #analysis #performance #predict #statistics #using
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis (RBB, NM, CO, LTP, MRM), pp. 332–337.
DAC-1993-PullelaMP #optimisation #reliability #using
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization (SP, NM, LTP), pp. 165–170.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.