Person: Noel Menezes

DBLP: Menezes:Noel

Contributed to:

2008

2007

2006

2005

2004

1999

1995

1994

1994

1993

Wrote 10 papers:

DAC-2008-MenezesKA #grid #power management #verification

A “true” electrical cell model for timing, noise, and power grid verification (NM, CVK, CSA), pp. 462–467.

DAC-2007-BurnsKMBTD #analysis #comparative #design #statistics

Comparative Analysis of Conventional and Statistical Design Techniques (SMB, MK, NM, KAB, JT, VD), pp. 238–243.

DAC-2006-AminKMKC #library #multi

A multi-port current source model for multiple-input switching effects in CMOS library cells (CSA, CVK, NM, KK, EC), pp. 247–252.

DAC-2005-AminMKDCHI #analysis #how #question #statistics

Statistical static timing analysis: how simple can we get? (CSA, NM, KK, FD, UC, NH, YII), pp. 652–657.

DAC-2004-NajmM #analysis #statistics

Statistical timing analysis based on a timing yield model (FNN, NM), pp. 460–465.

DAC-1999-ChenM #using

Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching (CPC, NM), pp. 502–506.

DAC-1995-MenezesPP #optimisation

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (NM, SP, LTP), pp. 690–695.

DAC-1994-DartuMQP #performance

A Gate-Delay Model for high-Speed CMOS Circuits (FD, NM, JQ, LTP), pp. 576–580.

EDAC-1994-BrashearMOPM #analysis #performance #predict #statistics #using

Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis (RBB, NM, CO, LTP, MRM), pp. 332–337.

DAC-1993-PullelaMP #optimisation #reliability #using

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization (SP, NM, LTP), pp. 165–170.