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Travelled to:
2 × USA
Collaborated with:
R.Wei J.Jou S.T.Chakradhar S.Dey M.Potkonjak C.Tseng M.M.Tong A.K.Bose
Talks about:
synthesi (2) behavior (2) circuit (2) delay (2) versatil (1) structur (1) sequenti (1) system (1) global (1) optim (1)

Person: Steven G. Rothweiler

DBLP DBLP: Rothweiler:Steven_G=

Contributed to:

DAC 19931993
DAC 19881988

Wrote 3 papers:

DAC-1993-ChakradharDPR #optimisation #using
Sequential Circuit Delay optimization Using Global Path Delays (STC, SD, MP, SGR), pp. 483–489.
DAC-1988-TsengWRTB #behaviour #named #synthesis
Bridge: A Versatile Behavioral Synthesis System (CJT, RSW, SGR, MMT, AKB), pp. 415–420.
DAC-1988-WeiRJ #behaviour #named #synthesis
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping (RSW, SGR, JYJ), pp. 409–414.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.