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Travelled to:
1 × Germany
1 × Spain
16 × USA
3 × France
Collaborated with:
A.Raghunathan L.Chen K.Lahiri N.K.Jha X.Bai S.Bhattacharya F.Brglez M.Potkonjak V.J.Kozhikkottu S.T.Chakradhar K.Sekar C.Zhao Y.Zhao K.D.Wagner K.Cheng G.Lakshminarayana C.N.Taylor J.Rajski I.Ghosh B.Sengupta G.Kedem R.Venkatesan S.Chandra S.Ravi F.Karim A.Nguyen R.R.Rao M.Rodgers K.Roy M.Lajolo L.Lavagno K.Wakabayashi S.G.Rothweiler Z.Iqbal A.C.Parker C.K.Verma M.Hart S.Bhatkar A.Parker-Wood A.Pan V.S.Pai A.Krstic W.Lai P.Sánchez Y.Cheng K.S.Khouri
Talks about:
chip (10) test (9) system (8) base (7) methodolog (6) design (6) power (6) optim (6) architectur (5) processor (5)

Person: Sujit Dey

DBLP DBLP: Dey:Sujit

Contributed to:

ICEIS v1 20152015
DAC 20142014
DAC 20122012
DATE 20112011
DAC 20072007
DATE 20062006
DAC 20052005
DAC 20042004
DAC 20032003
DAC 20022002
DAC 20012001
DAC 20002000
DATE 20002000
DAC 19991999
DAC 19981998
DAC 19971997
ED&TC 19971997
DAC 19961996
DAC 19941994
DAC 19931993
DAC 19901990

Wrote 34 papers:

ICEIS-v1-2015-VermaHBPD #enterprise #information management #predict #repository
Access Prediction for Knowledge Workers in Enterprise Data Repositories (CKV, MH, SB, APW, SD), pp. 150–161.
DAC-2014-KozhikkottuPPDR #clustering #parallel #source code #thread
Variation Aware Cache Partitioning for Multithreaded Programs (VJK, AP, VSP, SD, AR), p. 6.
DAC-2012-KozhikkottuDR #design
Recovery-based design for variation-tolerant SoCs (VJK, SD, AR), pp. 826–833.
DATE-2011-KozhikkottuVRD #analysis #named #performance #variability
VESPA: Variability emulation for System-on-Chip performance analysis (VJK, RV, AR, SD), pp. 2–7.
DAC-2007-ChandraLRD #power management
System-on-Chip Power Management Considering Leakage Power Variations (SC, KL, AR, SD), pp. 877–882.
DATE-2006-SekarLRD #adaptation #configuration management #platform
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms (KS, KL, AR, SD), pp. 728–733.
DAC-2005-SekarLRD #architecture #communication #configuration management #named
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology (KS, KL, AR, SD), pp. 571–574.
DAC-2005-ZhaoZD #constraints #robust
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits (CZ, YZ, SD), pp. 190–195.
DAC-2004-ZhaoBD #analysis #scalability
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits (CZ, XB, SD), pp. 894–899.
DAC-2003-ChenRRD #programmable #scalability #self
A scalable software-based self-test methodology for programmable processors (LC, SR, AR, SD), pp. 548–553.
DAC-2002-ChenD
Software-based diagnosis for processors (LC, SD), pp. 259–262.
DAC-2002-KrsticLCCD #design #embedded #self
Embedded software-based self-testing for SoC design (AK, WCL, KTC, LC, SD), pp. 355–360.
DAC-2002-LahiriDR #architecture #communication #design #performance #power management
Communication architecture based power management for battery efficient system design (KL, SD, AR), pp. 691–696.
DAC-2001-ChenBD #embedded #fault #testing #using
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores (LC, XB, SD), pp. 317–320.
DAC-2001-KarimNDR #architecture #communication #network
On-Chip Communication Architecture for OC-768 Network Processors (FK, AN, SD, RRR), pp. 678–683.
DAC-2001-TaylorDZ #energy #modelling
Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies (CNT, SD, YZ), pp. 754–757.
DAC-2000-BaiDR #self
Self-test methodology for at-speed test of crosstalk in chip interconnects (XB, SD, JR), pp. 619–624.
DAC-2000-ChenDSSC #embedded #hardware #self
Embedded hardware and software self-testing methodologies for processor cores (LC, SD, PS, KS, YC), pp. 625–630.
DAC-2000-ChuengDRR #challenge
Test challenges for deep sub-micron technologies (KTC, SD, MR, KR), pp. 142–149.
DAC-2000-LahiriRLD #architecture #communication #design
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips (KL, AR, GL, SD), pp. 513–518.
DATE-2000-LajoloRDL #design #performance
Efficient Power Co-Estimation Techniques for System-on-Chip Design (ML, AR, SD, LL), pp. 27–34.
DAC-1999-LakshminarayanaRKJD #optimisation #performance
Common-Case Computation: A High-Level Technique for Power and Performance Optimization (GL, AR, KSK, NKJ, SD), pp. 56–61.
DAC-1998-GhoshDJ #low cost #performance #testing
A Fast and Low Cost Testing Technique for Core-Based System-on-Chip (IG, SD, NKJ), pp. 542–547.
DAC-1997-RaghunathanDJW #control flow #design #power management
Power Management Techniques for Control-Flow Intensive Designs (AR, SD, NKJ, KW), pp. 429–434.
EDTC-1997-BhattacharyaDS #testing
An RTL methodology to enable low overhead combinational testing (SB, SD, BS), pp. 146–152.
DAC-1996-RaghunathanDJ #analysis #reduction
Glitch Analysis and Reduction in Register Transfer Level (AR, SD, NKJ), pp. 331–336.
DAC-1996-WagnerD #overview #perspective #synthesis #testing
High-Level Synthesis for Testability: A Survey and Perspective (KDW, SD), pp. 131–136.
DAC-1994-BhattacharyaDB #optimisation #resource management
Clock Period Optimization During Resource Sharing and Assignment (SB, SD, FB), pp. 195–200.
DAC-1994-BhattacharyaDB94a #analysis #optimisation #performance #specification
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications (SB, SD, FB), pp. 491–496.
DAC-1994-ChakradharD
Resynthesis and Retiming for Optimum Partial Scan (STC, SD), pp. 87–93.
DAC-1994-PotkonjakD #optimisation #resource management #testing #using
Optimizing Resource Utilization and Testability Using Hot Potato Techniques (MP, SD), pp. 201–205.
DAC-1993-ChakradharDPR #optimisation #using
Sequential Circuit Delay optimization Using Global Path Delays (STC, SD, MP, SGR), pp. 483–489.
DAC-1993-IqbalPDP #algebra #using
Critical Path Minimization Using Retiming and Algebraic Speed-Up (ZI, MP, SD, ACP), pp. 573–577.
DAC-1990-DeyBK #clustering
Corolla Based Circuit Partitioning and Resynthesis (SD, FB, GK), pp. 607–612.

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