BibSLEIGH — Proceedings of the 30th Design Automation Conference

Alfred E. Dunlop
Proceedings of the 30th Design Automation Conference
DAC, 1993.

SYS

@proceedings{DAC-1993,
	acmid         = "157485",
	address       = "Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA",
	editor        = "Alfred E. Dunlop",
	isbn          = "0-89791-577-1",
	publisher     = "{ACM Press}",
	title         = "{Proceedings of the 30th Design Automation Conference}",
	year          = 1993,
}

Contents (132 items)

DAC-1993-ChuML #finite #performance #state machine: An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State Machines (TAC, NM, CKCL), pp. 2–6.
DAC-1993-MoonB: Elimination of Dynamic hazards by Factoring (CWM, RKB), pp. 7–13.
DAC-1993-Leveugle #fault tolerance: Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes (RL), pp. 14–18.
DAC-1993-Tokarnia: Minimal Shift Counters and Frequency Division (AMT), pp. 19–24.
DAC-1993-ChoHMPS #algorithm #approximate #automaton #traversal: Algorithms for Approximate FSM Traversal (HC, GDH, EM, BP, FS), pp. 25–30.
DAC-1993-OhlrichEGS #algorithm #identification #morphism #named #performance #using: SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm (MO, CE, EG, LS), pp. 31–37.
DAC-1993-LadageL #algorithm #using: Resistance Extraction using a Routing Algorithm (LL, RL), pp. 38–42.
DAC-1993-LaiFW #data type #performance #query: HV/VH Trees: A New Spatial Data Structure for Fast Region Queries (GGL, DSF, DFW), pp. 43–47.
DAC-1993-GirczycC #design #quality #reuse: Increasing Design Quality and Engineering Productivity through Design Reuse (EFG, SC), pp. 48–53.
DAC-1993-ClarkeMZFY #scalability: Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping (EMC, KLM, XZ, MF, JY), pp. 54–60.
DAC-1993-SiegelMD #automation #design: Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs (PS, GDM, DLD), pp. 61–67.
DAC-1993-TsuiPD #composition #power management: Technology Decomposition and Mapping Targeting Low Power Dissipation (CYT, MP, AMD), pp. 68–73.
DAC-1993-TiwariAM: Technology Mapping for Lower Power (VT, PA, SM), pp. 74–79.
DAC-1993-PomeranzR #generative #incremental #learning #named #testing: INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning (IP, SMR), pp. 80–85.
DAC-1993-ChengK #automation #finite #functional #generative #state machine #testing #using: Automatic Functional Test Generation Using the Extended Finite State Machine Model (KTC, ASK), pp. 86–91.
DAC-1993-SantucciCG #behaviour #heuristic #using: Speed up of Behavioral A.T.P.G. using a Heuristic Criterion (JFS, ALC, NG), pp. 92–96.
DAC-1993-MotoharaHMMKSS #algorithm #matrix #traversal #using: A State Traversal Algorithm Using a State Covariance Matrix (AM, TH, MM, HM, KK, YS, SS), pp. 97–101.
DAC-1993-KajiharaPKR #effectiveness #fault #generative #logic #testing: Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits (SK, IP, KK, SMR), pp. 102–106.
DAC-1993-AgrawalAV #distributed #generative #testing: Sequential Circuit Test Generation on a Distributed System (PA, VDA, JV), pp. 107–111.
DAC-1993-ChangA #named #performance: VIPER: An Efficient Vigorously Sensitizable Path Extractor (HC, JAA), pp. 112–117.
DAC-1993-HuangPS #approach #approximate #heuristic #polynomial #problem: A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem (STH, TMP, JMS), pp. 118–122.
DAC-1993-KawarabayashiSS #verification: A Verification Technique for Gated Clock (MK, NVS, ALSV), pp. 123–127.
DAC-1993-LamBS #modelling #using: Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions (WKCL, RKB, ALSV), pp. 128–134.
DAC-1993-JoneF #identification #optimisation: Timing Optimization By Gate Resizing And Critical Path Identification (WBJ, CLF), pp. 135–140.
DAC-1993-GraebWA #analysis #optimisation #worst-case: Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances (HEG, CUW, KA), pp. 142–147.
DAC-1993-Nagaraj #optimisation #performance: A New Optimizer for Performance Optimization of Analog Integrated Circuits (NSN), pp. 148–153.
DAC-1993-DharchoudhuryK #variability #worst-case: Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits (AD, SMK), pp. 154–158.
DAC-1993-LiuCS #behaviour #simulation #using #verification: Analog System Verification in the Presence of Parasitics Using Behavioral Simulation (EWYL, HCC, ALSV), pp. 159–163.
DAC-1993-PullelaMP #optimisation #reliability #using: Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization (SP, NM, LTP), pp. 165–170.
DAC-1993-LimCW #performance: Performance Oriented Rectilinear Steiner Trees (AL, SWC, CTW), pp. 171–176.
DAC-1993-HongXKCH #algorithm: Performance-Driven Steiner Tree Algorithm for Global Routing (XH, TX, ESK, CKC, JH), pp. 177–181.
DAC-1993-BoeseKR: High-Performance Routing Trees With Identified Critical Sinks (KDB, ABK, GR), pp. 182–187.
DAC-1993-ChenCHK #array: The Sea-of-Wires Array Aynthesis System (IYC, GLC, FJH, SYK), pp. 188–193.
DAC-1993-VemuriMSKRV #case study #experience #functional #synthesis #validation: Experiences in Functional Validation of a High Level Synthesis System (RV, PM, PS, NK, JR, RV), pp. 194–201.
DAC-1993-WooK #clustering #implementation #multi #performance: An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation. (NSW, JK), pp. 202–207.
DAC-1993-SawkarT #performance: Performance Directed Technology Mapping for Look-Up Table Based FPGAs (PS, DET), pp. 208–212.
DAC-1993-CongD #on the #trade-off: On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping (JC, YD), pp. 213–218.
DAC-1993-Mehendale #design #evaluation #independence #logic #named: MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs (MM), pp. 219–223.
DAC-1993-MurgaiBS #array #programmable #synthesis: Sequential Synthesis for Table Look Up Programmable Gate Arrays (RM, RKB, ALSV), pp. 224–229.
DAC-1993-VaishnavP #optimisation: Routability-Driven Fanout Optimization (HV, MP), pp. 230–235.
DAC-1993-ChickermaneRBP: Non-Scan Design-for-Testability Techniques for Sequential Circuits (VC, EMR, PB, JHP), pp. 236–241.
DAC-1993-SrinivasanGB #clustering #performance #pseudo #testing: An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing (RS, SKG, MAB), pp. 242–248.
DAC-1993-KagarisT: Partial Scan with Retiming (DK, ST), pp. 249–254.
DAC-1993-ParikhA #approach #cost analysis: A Cost-Based Approach to Partial Scan (PSP, MA), pp. 255–259.
DAC-1993-MatsunagaMB #on the #transitive: On Computing the Transitive Closure of a State Transition Relation (YM, PCM, RKB), pp. 260–265.
DAC-1993-HuD #dependence #functional: Reducing BDD Size by Exploiting Functional Dependencies (AJH, DLD), pp. 266–271.
DAC-1993-Minato #combinator #problem #set: Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems (SiM), pp. 272–277.
DAC-1993-LauK #modelling: Information Modelling of EDIF (RYWL, HJK), pp. 278–283.
DAC-1993-NouraniP #algorithm #estimation #layout: A Layout Estimation Algorithm for RTL Datapaths (MN, CAP), pp. 285–291.
DAC-1993-LeeJW #behaviour #synthesis: Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments (TCL, NKJ, WW), pp. 292–297.
DAC-1993-KimL #multi #synthesis: Utilization of Multiport Memories in Data Path Synthesis (TK, CLL), pp. 298–302.
DAC-1993-GhoshNSP #architecture #multi #synthesis: Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving (DG, SKN, PS, KP), pp. 303–307.
DAC-1993-RajaramanW #clustering: Optimal Clustering for Delay Minimization (RR, DFW), pp. 309–314.
DAC-1993-KuznarBK #multi: Cost Minimization of Partitions into Multiple Devices (RK, FB, KK), pp. 315–320.
DAC-1993-NagR #performance: Iterative Wirability and Performance Improvement for FPGAs (SN, KR), pp. 321–325.
DAC-1993-ChanSZ #array #on the #predict #programmable: On Routability Prediction for Field-Programmable Gate Arrays (PKC, MDFS, JYZ), pp. 326–330.
DAC-1993-Nurnberger #policy: The Clinton/Gore Technology Policies (RDN), pp. 331–335.
DAC-1993-WangDNS #architecture #multi #scalability #synthesis #using: High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules (HW, NDD, AN, KYS), pp. 336–342.
DAC-1993-ChatterjeeR #architecture #composition #multi #optimisation: An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition (AC, RKR), pp. 343–348.
DAC-1993-SharmaJ #named #scheduling: InSyn: Integrated Scheduling for DSP Applications (AS, RJ), pp. 349–354.
DAC-1993-SharmaJ93a #architecture #performance #synthesis: Estimating Architectural Resources and Performance for High-Level Synthesis Applications (AS, RJ), pp. 355–360.
DAC-1993-CarlsonC #order #performance: Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering (BSC, CYRC), pp. 361–366.
DAC-1993-YuanPR #component #evaluation #logic #simulation: Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation (DCY, LTP, JTR), pp. 367–372.
DAC-1993-Gennart #comparative #design #validation: Comparative Design Validation Based on Event Pattern Mappings (BAG), pp. 373–378.
DAC-1993-StamoulisH #correlation #probability #simulation: Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects (GIS, INH), pp. 379–383.
DAC-1993-KriplaniNYH #correlation: Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits (HK, FNN, PY, INH), pp. 384–388.
DAC-1993-BamjiV #constraints #identification #named: MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction (CB, RV), pp. 389–394.
DAC-1993-YaoCDNL #using: Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP (SZY, CKC, DD, SN, CYL), pp. 395–400.
DAC-1993-PanDL #constraints #graph #layout #reduction: Optimal Graph Constraint Reduction for Symbolic Layout Compaction (PP, SkD, CLL), pp. 401–406.
DAC-1993-DaoMHOM: A Compaction Method for Full Chip VLSI Layouts (JD, NM, TH, CO, SM), pp. 407–412.
DAC-1993-ChaiyakulGR: High-Level Transformations for Minimizing Syntactic Variances (VC, DG, LR), pp. 413–418.
DAC-1993-PapachristouHN #approach #synthesis: An Approach for Redesigning in Data Path Synthesis (CAP, HH, MN), pp. 419–423.
DAC-1993-SeawrightB #performance #synthesis: High-Level Symbolic Construction Technique for High Performance Sequential Synthesis (AS, FB), pp. 424–428.
DAC-1993-KarriO #architecture #synthesis: High-Level Synthesis of Fault-Secure Microarchitectures (RK, AO), pp. 429–433.
DAC-1993-HaworthB #design #towards: Towards Optimal System-Level Design (MSH, WPB), pp. 434–438.
DAC-1993-PomeranzRU #fault #generative #named #testing: NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits (IP, SMR, PU), pp. 439–445.
DAC-1993-LamSBS #fault #performance #trade-off: Delay Fault Coverage and Performance Tradeoffs (WKCL, AS, RKB, ALSV), pp. 446–452.
DAC-1993-ChakrabortyAB #design #fault #testing: Design for Testability for Path Delay faults in Sequential Circuits (TJC, VDA, MLB), pp. 453–457.
DAC-1993-ChessL #fault #simulation: Bridge Fault simulation strategies for CMOS integrated Circuits (BC, TL), pp. 458–462.
DAC-1993-RhoSP #finite #sequence #state machine: Minimum Length Synchronizing Sequences of Finite State Machine (JKR, FS, CP), pp. 463–468.
DAC-1993-JoyceS #evaluation #interactive #symbolic computation: Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving (JJJ, CJHS), pp. 469–474.
DAC-1993-HojatiSBK #approach #model checking: A Unified Approach to Language Containment and Fair CTL Model Checking (RH, TRS, RKB, RPK), pp. 475–481.
DAC-1993-ChakradharDPR #optimisation #using: Sequential Circuit Delay optimization Using Global Path Delays (STC, SD, MP, SGR), pp. 483–489.
DAC-1993-ShenoyBS #multi #pipes and filters: Resynthesis of Multi-Phase Pipelines (NVS, RKB, ALSV), pp. 490–496.
DAC-1993-PapaefthymiouR #named: TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry (MCP, KHR), pp. 497–502.
DAC-1993-ChungWH #design #fault #logic: Diagnosis and Correction of Logic Design Errors in Digital Circuits (PYC, YMW, INH), pp. 503–508.
DAC-1993-NagiCA #fault #named: DRAFTS: Discretized Analog Circuit Fault Simulator (NN, AC, JAA), pp. 509–514.
DAC-1993-MeyerC #fault #multi #performance #simulation: Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy (WM, RC), pp. 515–519.
DAC-1993-ChakravartyG #algorithm #fault: An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits (SC, YG), pp. 520–524.
DAC-1993-Lee #2d #algorithm #bound #design: A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules (TcL), pp. 525–530.
DAC-1993-HamadaCC #approach #linear #named #network #using: Prime: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach (TH, CKC, PMC), pp. 531–536.
DAC-1993-ChoS #algorithm #performance: A Nuffer Distribution Algorithm for High-Speed Clock Routing (JDC, MS), pp. 537–543.
DAC-1993-MogakiSKH #approach #layout: Cooperative Approach to a Practical Analog LSI Layout System (MM, YS, MK, TH), pp. 544–549.
DAC-1993-GanapathyA #pseudo: Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor (GG, JAA), pp. 550–555.
DAC-1993-WanG #layout #named: ABLE: AMD Backplane for Layout Engines (KWW, RAG), pp. 556–560.
DAC-1993-Duvall #design #statistics: Practical Statistical Design of Complex Integrated Circuit Products (SGD), pp. 561–565.
DAC-1993-ChaoLS #algorithm #pipes and filters #scheduling: Rotation Scheduling: A Loop Pipelining Algorithm (LFC, ASL, EHMS), pp. 566–572.
DAC-1993-IqbalPDP #algebra #using: Critical Path Minimization Using Retiming and Algebraic Speed-Up (ZI, MP, SD, ACP), pp. 573–577.
DAC-1993-HuangJHHW #algorithm #scheduling: A Tree-Based Scheduling Algorithm for Control-Dominated Circuits (SHH, YLJ, CTH, YCH, JFW), pp. 578–582.
DAC-1993-CloutierT #pipes and filters #set #synthesis: Synthesis of Pipelined Instruction Set Processors (RJC, DET), pp. 583–588.
DAC-1993-KhooC #multi #performance: An Efficient Multilayer MCM Router Based on Four-Via Routing (KYK, JC), pp. 590–595.
DAC-1993-HuangHCK #algorithm #performance: An Efficient Timing-Driven Global Routing Algorithm (JH, XH, CKC, ESK), pp. 596–600.
DAC-1993-LewisP: A Negative Reinforcement Method for PGA Routing (FDL, WCCP), pp. 601–605.
DAC-1993-CongLZ #design #distributed: Performance-Driven Interconnect Design Based on Distributed RC Delay Model (JC, KSL, DZ), pp. 606–611.
DAC-1993-Edahiro #algorithm #clustering #optimisation: A Clustering-Based Optimization Algorithm in Zero-Skew Routings (ME), pp. 612–616.
DAC-1993-McGeerSBS #logic #named: Espresso-Signature: A New Exact Minimizer for Logic Functions (PCM, JVS, RKB, ALSV), pp. 618–624.
DAC-1993-CoudertMF #logic: A New Viewpoint on Two-Level Logic Minimization (OC, JCM, HF), pp. 625–630.
DAC-1993-DamianiYM #logic #optimisation: Optimization of Combinational Logic Circuits Based on Compatible Gates (MD, JCYY, GDM), pp. 631–636.
DAC-1993-EvekingH #optimisation: Optimization and Resynthesis of Complex Data-Paths (HE, SH), pp. 637–641.
DAC-1993-LaiPV #composition #logic #synthesis: BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis (YTL, MP, SBKV), pp. 642–647.
DAC-1993-SuttonBD #design #using: Design Management Using Dynamically Defined Flows (PRS, JBB, SWD), pp. 648–653.
DAC-1993-SilvaK #design #documentation #interface: Active Documentation: A New Interface for VLSI Design (MJS, RHK), pp. 654–660.
DAC-1993-MandayamV #attribute grammar #performance #specification #using: Performance Specification Using Attributed Grammars (RM, RV), pp. 661–667.
DAC-1993-GiumaleK: An Information Model of Time (CAG, HJK), pp. 668–672.
DAC-1993-Kra #co-evolution #design #hardware: A Cross-Debugging Method for Hardware/Software Co-design Environments (YK), pp. 673–677.
DAC-1993-KamonTW #3d #multi #named: FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program (MK, MJT, JW), pp. 678–683.
DAC-1993-ChouCC #finite #modelling #performance #simulation #using: High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods (TYC, JC, ZJC), pp. 684–690.
DAC-1993-SriramK #approximate #performance: Fast Approximation of the Transient Response of Lossy Transmision Line Trees (MS, SMK), pp. 691–696.
DAC-1993-HaqueC #analysis #design #distributed #reliability: Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections (MH, SC), pp. 697–701.
DAC-1993-HeebPR #modelling #using: Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits (HH, SP, AER), pp. 702–706.
DAC-1993-Yarnikh: The State of CAD and VLSI in Russia (VY), pp. 707–708.
DAC-1993-Tatarnikov: The State of VHDL in Russia (YT), pp. 709–711.
DAC-1993-Birger #simulation: The State of Simulation in Russia (AB), pp. 712–715.
DAC-1993-Mikhov: The State of EDA in Russian Universities (VMM), pp. 716–719.
DAC-1993-YangLYD #performance #simulation: An Efficient Non-Quasi-Static Diode Model for Circuit Simulation (ATY, YL, JTY, RRD), pp. 720–725.
DAC-1993-LiaoDWC #metaprogramming #network #polynomial #using: S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function (HL, WWMD, RW, FYC), pp. 726–731.
DAC-1993-ChiproutN #evaluation #performance: Addressing High-Speed Interconnect Issues in Asymptotic Waveform Evaluation (EC, MSN), pp. 732–736.
DAC-1993-VisweswariahW #incremental #simulation: Incremental Event-Driven Simulation of Digital FET Circuits (CV, JAW), pp. 737–741.
DAC-1993-AlpertK #clustering #geometry #multi #performance: Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning (CJA, ABK), pp. 743–748.
DAC-1993-ChanSZ93a #clustering: Spectral K-Way Ratio-Cut Partitioning and Clustering (PKC, MDFS, JYZ), pp. 749–754.
DAC-1993-CongS #algorithm #bottom-up #clustering #design #parallel: A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design (JC, MS), pp. 755–760.
DAC-1993-ShihK #clustering #polynomial #programming: Quadratic Boolean Programming for Performance-Driven System Partitioning (MS, ESK), pp. 761–765.

Alfred E. DunlopProceedings of the 30th Design Automation ConferenceDAC, 1993.

Contents (132 items)

Alfred E. Dunlop
Proceedings of the 30th Design Automation Conference
DAC, 1993.