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Travelled to:
1 × France
1 × USA
Collaborated with:
A.Agarwal H.Sampath R.Vemuri
Talks about:
parasit (2) capacit (2) accur (2) circuit (1) layout (1) analog (1) model (1) estim (1) fast (1) awar (1)

Person: Veena Yelamanchili

DBLP DBLP: Yelamanchili:Veena

Contributed to:

DAC 20042004
DATE v2 20042004

Wrote 2 papers:

DAC-2004-AgarwalSYV #modelling #performance
Fast and accurate parasitic capacitance models for layout-aware (AA, HS, VY, RV), pp. 145–150.
DATE-v2-2004-AgarwalSYV #estimation
Accurate Estimation of Parasitic Capacitances in Analog Circuits (AA, HS, VY, RV), pp. 1364–1365.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.