BibSLEIGH — Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 2

Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 2
DATE v2, 2004.

SYS

@proceedings{DATE-v2-2004,
	address       = "Paris, France",
	isbn          = "0-7695-2085-5",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 2}",
	year          = 2004,
}

Contents (122 items)

DATE-v2-2004-MangoCWC #fault #testing: Pattern Selection for Testing of Deep Sub-Micron Timing Defects (MCTC, LCW, KTC), p. 160.
DATE-v2-2004-LoghiABBZ #communication: Analyzing On-Chip Communication in a MPSoC Environment (ML, FA, DB, LB, RZ), pp. 752–757.
DATE-v2-2004-GrunewaldNPR #multi #network: A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC (MG, JCN, MP, UR), pp. 758–763.
DATE-v2-2004-PestanaRRGG #approach #network #trade-off: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach (SGP, ER, AR, KGWG, OPG), pp. 764–769.
DATE-v2-2004-XuWHCL #case study #design #embedded #video: A Case Study in Networks-on-Chip Design for Embedded Video (JX, WW, JH, STC, TL), pp. 770–777.
DATE-v2-2004-DuanK: Exploiting Crosstalk to Speed up On-Chip Buse (CD, SPK), pp. 778–783.
DATE-v2-2004-GlebovGZOPB #analysis: False-Noise Analysis for Domino Circuits (AG, SG, VZ, CO, RP, MRB), pp. 784–789.
DATE-v2-2004-LiuWH #logic #synthesis: Crosstalk Minimization in Logic Synthesis for PLA (YYL, KHW, TH), pp. 790–795.
DATE-v2-2004-NardiS #synthesis: Synthesis for Manufacturability: A Sanity Check (AN, ALSV), pp. 796–803.
DATE-v2-2004-AbasRK #design #metric: Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit (MAA, GR, DJK), pp. 804–809.
DATE-v2-2004-VrankenSW #layout: Impact of Test Point Insertion on Silicon Area and Timing during Layout (HPEV, FSS, HJW), pp. 810–815.
DATE-v2-2004-RizkPW #design #embedded #source code: Designing Self Test Programs for Embedded DSP Cores (HR, CAP, FGW), pp. 816–823.
DATE-v2-2004-WangMR #automation #megamodelling #predict: Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction (ZW, RM, JSR), pp. 824–829.
DATE-v2-2004-WangTC #network #optimisation: Thermal and Power Integrity Based Power/Ground Networks Optimization (TYW, JLT, CCPC), pp. 830–835.
DATE-v2-2004-LanD #analysis #modelling #synthesis: Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs (HL, RWD), pp. 836–843.
DATE-v2-2004-KadayifK #energy #network: Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks (IK, MTK), pp. 852–857.
DATE-v2-2004-AcquavivaLB #network #power management: Power-Aware Network Swapping for Wireless Palmtop PCs (AA, EL, AB), pp. 858–863.
DATE-v2-2004-LiverisB #design #interface #power management #synthesis: Power Aware Interface Synthesis for Bus-Based SoC Design (NDL, PB), pp. 864–869.
DATE-v2-2004-BranoverKG #design: Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones (AB, RK, RG), pp. 870–877.
DATE-v2-2004-RadulescuDGRW #abstraction #flexibility #interface #network #performance: An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration (AR, JD, KGWG, ER, PW), pp. 878–883.
DATE-v2-2004-JalabertMBM #network: ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip (AJ, SM, LB, GDM), pp. 884–889.
DATE-v2-2004-MillbergNTJ #network #using: Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip (MM, EN, RT, AJ), pp. 890–895.
DATE-v2-2004-MuraliM #architecture: Bandwidth-Constrained Mapping of Cores onto NoC Architectures (SM, GDM), pp. 896–903.
DATE-v2-2004-ZhangGZJ #logic #network #optimisation #synthesis: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies (RZ, PG, LZ, NKJ), pp. 904–909.
DATE-v2-2004-KarandikarS #implementation #performance: Fast Comparisons of Circuit Implementations (SKK, SSS), pp. 910–915.
DATE-v2-2004-TiwariT #embedded #finite #memory management #state machine: Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs (AT, KAT), pp. 916–921.
DATE-v2-2004-KumarBK #algorithm #analysis #array #embedded #memory management #named #reduction #using: MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis (AMK, JB, VK), pp. 922–929.
DATE-v2-2004-RajskiT #design #question #requirements #what: Nanometer Design: What are the Requirements for Manufacturing Test? (JR, KT), pp. 930–937.
DATE-v2-2004-PhillipsS #reduction: Poor Man’s TBR: A Simple Model Reduction Scheme (JRP, LMS), pp. 938–943.
DATE-v2-2004-Feldmann #linear #order #reduction #scalability: Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals (PF), pp. 944–947.
DATE-v2-2004-JiangC #named: SCORE: SPICE COmpatible Reluctance Extraction (RJ, CCPC), pp. 948–953.
DATE-v2-2004-RosselloS: A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk (JLR, JS), pp. 954–961.
DATE-v2-2004-DasikaVCS #framework: A Framework for Battery-Aware Sensor Management (SD, SBKV, KC, RS), pp. 962–967.
DATE-v2-2004-Stanley-MarbellM #adaptation #fault tolerance: Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance (PSM, DM), pp. 968–973.
DATE-v2-2004-GuptaJ #algorithm #architecture: An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology (PG, NKJ), pp. 974–979.
DATE-v2-2004-ShendeMB #communication #quantum: Smaller Two-Qubit Circuits for Quantum Communication and Computation (VVS, ILM, SSB), pp. 980–987.
DATE-v2-2004-VerbauwhedeSPK #architecture #design #embedded #energy #multi #performance: Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing (IV, PS, CP, BK), pp. 988–995.
DATE-v2-2004-VorgRR #cost analysis #metric: Measurement of IP Qualification Costs and Benefits (AV, MR, WR), pp. 996–1001.
DATE-v2-2004-UedaSTI #architecture #embedded #estimation #performance: Architecture-Level Performance Estimation for IP-Based Embedded Systems (KU, KS, YT, MI), pp. 1002–1007.
DATE-v2-2004-SinghT #architecture #multi: Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures (MS, MT), pp. 1008–1013.
DATE-v2-2004-BoladoPCHSSFB #framework #industrial #open source #platform: Platform Based on Open-Source Cores for Industrial Applications (MB, HP, JC, PH, PS, CS, HF, FB), pp. 1014–1019.
DATE-v2-2004-CheungPHC #equivalence #named #using: MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor (NC, SP, JH, JC), pp. 1020–1027.
DATE-v2-2004-PopEPIHB #clustering #design #embedded #multi #optimisation #realtime: Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application (PP, PE, ZP, VI, MH, OB), pp. 1027–1033.
DATE-v2-2004-TanM #analysis #multi #realtime: Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches (YT, VJMI), pp. 1034–1039.
DATE-v2-2004-MaxiaguineKT #execution: Workload Characterization Model for Tasks with Variable Execution Demand (AM, SK, LT), pp. 1040–1045.
DATE-v2-2004-JersakHE #analysis #design #embedded #performance: Context-Aware Performance Analysis for Efficient Embedded System Design (MJ, RH, RE), pp. 1046–1051.
DATE-v2-2004-ShoganC: Compact Binaries with Code Compression in a Software Dynamic Translator (SS, BRC), pp. 1052–1059.
DATE-v2-2004-DworakCWM #detection #fault: Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects (JD, BC, JW, MRM), pp. 1066–1071.
DATE-v2-2004-HuangCHTHH #analysis #fault #probability: Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis (YH, WTC, CJH, HYT, AH, YTH), pp. 1072–1077.
DATE-v2-2004-TirumurtiKSC #approach #modelling #power management: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit (CT, SK, SSK, YSC), pp. 1078–1083.
DATE-v2-2004-Al-ArsG #fault #in memory #memory management #testing: Soft Faults and the Importance of Stresses in Memory Testing (ZAA, AJvdG), pp. 1084–1091.
DATE-v2-2004-LinZ #fixpoint: Wire Retiming for System-on-Chip by Fixpoint Computation (CL, HZ), pp. 1092–1097.
DATE-v2-2004-KahngMR #named: Boosting: Min-Cut Placement with Improved Signal Delay (ABK, ILM, SR), pp. 1098–1103.
DATE-v2-2004-DengW #algorithm: Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus (LD, MDFW), pp. 1104–1109.
DATE-v2-2004-GuptaK #performance #statistics: A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk (SG, SK), pp. 1110–1115.
DATE-v2-2004-XiongH #multi: Full-Chip Multilevel Routing for Power and Signal Integrity (JX, LH), pp. 1116–1123.
DATE-v2-2004-AntwerpenDGMPVV #design #energy #multi: Energy-Aware System Design for Wireless Multimedia (HVA, NDD, RKG, SM, CP, NV, RvV), pp. 1124–1131.
DATE-v2-2004-DziriCWJ #component #design #integration #multi #validation: Unified Component Integration Flow for Multi-Processor SoC Design and Validation (MAD, WOC, FRW, AAJ), pp. 1132–1137.
DATE-v2-2004-ChandraXSP #design #performance: An Interconnect Channel Design Methodology for High Performance Integrated Circuits (VC, AX, HS, LTP), pp. 1138–1143.
DATE-v2-2004-BobrekPNPT #approach #hybrid #modelling #simulation #using: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach (AB, JJP, JEN, JMP, DET), pp. 1144–1149.
DATE-v2-2004-SuhBL #multi: Supporting Cache Coherence in Heterogeneous Multiprocessor Systems (TS, DMB, HHSL), pp. 1150–1157.
DATE-v2-2004-KadayifKK #energy #multi: Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors (IK, MTK, IK), pp. 1158–1163.
DATE-v2-2004-PinelloCS #deployment #embedded #fault tolerance #realtime: Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications (CP, LPC, ALSV), pp. 1164–1169.
DATE-v2-2004-ZhangC #analysis #embedded #fault tolerance #realtime #scalability: Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems (YZ, KC), pp. 1170–1175.
DATE-v2-2004-CortesEP #realtime #scheduling: Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks (LAC, PE, ZP), pp. 1176–1183.
DATE-v2-2004-SunterOCJBEBB #standard #testing: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 (SKS, AO, AC, NJ, DB, BE, CB, BB), pp. 1184–1191.
DATE-v2-2004-RanKWM #analysis: Eliminating False Positives in Crosstalk Noise Analysis (YR, AK, YW, MMS), pp. 1192–1197.
DATE-v2-2004-MondalCM #analysis #approach #logic #using: A New Approach to Timing Analysis Using Event Propagation and Temporal Logic (AM, PPC, CAM), pp. 1198–1203.
DATE-v2-2004-HsiehH #design #effectiveness: A New Effective Congestion Model in Floorplan Design (YLH, TMH), pp. 1204–1209.
DATE-v2-2004-NakashimaIOM: ULSI Interconnect Length Distribution Model Considering Core Utilization (HN, JI, KO, KM), pp. 1210–1217.
DATE-v2-2004-RosaPGL #configuration management #framework #implementation #platform: Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform (ALR, CP, FG, LL), pp. 1218–1223.
DATE-v2-2004-MeiVVL #architecture #case study #configuration management #design #matrix: Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study (BM, SV, DV, RL), pp. 1224–1229.
DATE-v2-2004-KhawamBPAAAW #array #configuration management #implementation #mobile #performance #video: Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays (SK, SB, AP, IA, NA, TA, FW), pp. 1230–1235.
DATE-v2-2004-Krupnova #experience #industrial #multi: Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience (HK), pp. 1236–1243.
DATE-v2-2004-ZhuM #architecture #communication #framework #multi #platform #prototype #specification #using: Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing (XZ, SM), pp. 1244–1249.
DATE-v2-2004-BanerjeeVC #architecture #performance: A Power and Performance Model for Network-on-Chip Architectures (NB, PV, KSC), pp. 1250–1255.
DATE-v2-2004-WieferinkKLAMBN #communication #framework #multi #platform: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform (AW, TK, RL, GA, HM, GB, AN), pp. 1256–1263.
DATE-v2-2004-VermaWM #algorithm: Cache-Aware Scratchpad Allocation Algorithm (MV, LW, PM), pp. 1264–1269.
DATE-v2-2004-LorenzM #algorithm #code generation #search-based #using: Phase Coupled Code Generation for DSPs Using a Genetic Algorithm (ML, PM), pp. 1270–1275.
DATE-v2-2004-HohenauerSKWKLAMBS #c #compilation #generative #modelling: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models (MH, HS, KK, OW, TK, RL, GA, HM, GB, HvS), pp. 1276–1283.
DATE-v2-2004-TehranipourNC #flexibility #testing: Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression (MHT, MN, KC), pp. 1284–1289.
DATE-v2-2004-ArslanO #architecture #named #reduction: CircularScan: A Scan Architecture for Test Cost Reduction (BA, AO), pp. 1290–1295.
DATE-v2-2004-WangLC #fault #hardware #hybrid #testing: Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets (SW, XL, STC), pp. 1296–1301.
DATE-v2-2004-LeiningerGM #configuration management #using: Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Code (AL, MG, PM), pp. 1302–1309.
DATE-v2-2004-WanS #compilation #multi #simulation: Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation (BW, CJRS), pp. 1310–1315.
DATE-v2-2004-FengZCZF #analysis #order #reduction: Direct Nonlinear Order Reduction with Variational Analysis (LF, XZ, CC, DZ, QF), pp. 1316–1321.
DATE-v2-2004-ZhouZLLZC #analysis #using: Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method (XZ, DZ, JL, RL, XZ, CC), pp. 1322–1326.
DATE-v2-2004-MineKKWA #hybrid #linear #performance #reduction #simulation: Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits (TM, HK, AK, TW, HA), pp. 1327–1333.
DATE-v2-2004-Fitzpatric: System Verilog for VHDL Users (TF), pp. 1334–1341.
DATE-v2-2004-MarculescuPH #design #distributed #multi #perspective: Distributed Multimedia System Design: A Holistic Perspective (RM, MP, JH), pp. 1342–1349.
DATE-v2-2004-SbeytiNE #adaptation #embedded #multi: Adaptive Prefetching for Multimedia Applications in Embedded Systems (HS, SN, LE), pp. 1350–1351.
DATE-v2-2004-PisharathCK #approach #database #execution #in memory #query: Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases (JP, ANC, MTK), pp. 1352–1353.
DATE-v2-2004-ViamontesMH #quantum #simulation: High-Performance QuIDD-Based Simulation of Quantum Circuits (GFV, ILM, JPH), pp. 1354–1355.
DATE-v2-2004-ReedLBMC #algorithm #parallel #simulation: An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation (DKR, SPL, JB, JAM, DMC), pp. 1356–1357.
DATE-v2-2004-HuangTL #fault tolerance #programmable: Fault Tolerance of Programmable Switch Blocks (JH, MBT, FL), pp. 1358–1359.
DATE-v2-2004-SogomonyanMOG #self: A New Self-Checking Sum-Bit Duplicated Carry-Select Adder (ESS, DM, VO, MG), pp. 1360–1361.
DATE-v2-2004-ElviraMAG #generative #megamodelling #performance #simulation: A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation (LE, FM, XA, JLG), pp. 1362–1363.
DATE-v2-2004-AgarwalSYV #estimation: Accurate Estimation of Parasitic Capacitances in Analog Circuits (AA, HS, VY, RV), pp. 1364–1365.
DATE-v2-2004-CrisuCVL #development #embedded #framework #named: GRAAL — A Development Framework for Embedded Graphics Accelerators (DC, SC, SV, PL), pp. 1366–1367.
DATE-v2-2004-CortadellaKLLS #approach #automation: From Synchronous to Asynchronous: An Automatic Approach (JC, AK, LL, KL, CPS), pp. 1368–1369.
DATE-v2-2004-LaouamriA #network #protocol #testing #using: Enhancing Testability of System on Chips Using Network Management Protocols (OL, CA), pp. 1370–1371.
DATE-v2-2004-LampropoulosAR #using: Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique (ML, BMAH, PMR), pp. 1372–1373.
DATE-v2-2004-AragonNVB #design #embedded #energy: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors (JLA, DN, AVV, AMB), pp. 1374–1375.
DATE-v2-2004-NaculG #configuration management #power management: Dynamic Voltage and Cache Reconfiguration for Low Power (ACN, TG), pp. 1376–1379.
DATE-v2-2004-GoudarziHM #implementation #modelling #morphism #object-oriented #polymorphism: Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models (MG, SH, AM), pp. 1380–1381.
DATE-v2-2004-YooYBJD #concept #design #multi #using: Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software (SY, MWY, AB, AAJ, MDN), pp. 1382–1383.
DATE-v2-2004-AgrawalJ #logic #synthesis: Synthesis of Reversible Logic (AA, NKJ), pp. 1384–1385.
DATE-v2-2004-ZieglerS #design #parallel: A Unified Design Space for Regular Parallel Prefix Adders (MMZ, MRS), pp. 1386–1387.
DATE-v2-2004-JabirP #diagrams #multi #named #representation: MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions (AMJ, DKP), pp. 1388–1389.
DATE-v2-2004-CasuM #implementation #latency #protocol: Issues in Implementing Latency Insensitive Protocols (MRC, LM), pp. 1390–1391.
DATE-v2-2004-SchattkowskyM #embedded #execution #modelling #realtime #specification: Model-Based Specification and Execution of Embedded Real-Time Systems (TS, WM), pp. 1392–1393.
DATE-v2-2004-Singh #co-evolution #design: A Demonstration of Co-Design and Co-Verification in a Synchronous Language (SS), pp. 1394–1395.
DATE-v2-2004-ZhouCK #embedded: Profile Guided Management of Code Partitions for Embedded Systems (SZ, BRC, NK), pp. 1396–1399.
DATE-v2-2004-JiangC04a #reduction: Realizable Reduction for Electromagnetically Coupled RLMC Interconnects (RJ, CCPC), pp. 1400–1401.
DATE-v2-2004-GarceaMKO #statistics: Statistically Aware Buffer Planning (GSG, NPvdM, KJvdK, RHJMO), pp. 1402–1403.
DATE-v2-2004-BernardiniPM: A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology (SB, JMP, PM), pp. 1404–1405.
DATE-v2-2004-VazquezG #fault #monitoring #power management: Power Supply Noise Monitor for Signal Integrity Faults (JRV, JPdG), pp. 1406–1407.
DATE-v2-2004-TahooriL #automaton #design #quantum #testing: Testing of Quantum Dot Cellular Automata Based Designs (MBT, FL), pp. 1408–1409.
DATE-v2-2004-MinzPL #3d: Net and Pin Distribution for 3D Package Global Routing (JRM, MP, SKL), pp. 1410–1411.
DATE-v2-2004-OlbrichB #locality #probability #using: Placement Using a Localization Probability Model (LPM) (MO, EB), p. 1412.
DATE-v2-2004-GuilleyHMPP #hardware: CMOS Structures Suitable for Secured Hardware (SG, PH, YM, RP, JP), pp. 1414–1415.
DATE-v2-2004-RahimiBD #adaptation #optimisation: Timing Correction and Optimization with Adaptive Delay Sequential Element (KR, SB, CD), p. 1416.

Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 2DATE v2, 2004.

Contents (122 items)

Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 2
DATE v2, 2004.