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Travelled to:
1 × Ireland
2 × Canada
9 × USA
Collaborated with:
S.Pande M.J.Serrano T.Zhang J.Choi C.Lau S.Kim H.W.Cain
Talks about:
processor (5) context (3) regist (3) effici (3) optim (3) embed (3) alloc (3) call (3) differenti (2) network (2)

Person: Xiaotong Zhuang

DBLP DBLP: Zhuang:Xiaotong

Contributed to:

CGO 20092009
ISMM 20092009
CGO 20082008
CGO 20062006
LCTES 20062006
PLDI 20062006
CGO 20052005
PLDI 20052005
ASPLOS 20042004
LCTES 20042004
PLDI 20042004
LCTES 20032003

Wrote 13 papers:

CGO-2009-SerranoZ #approximate
Building Approximate Calling Context from Partial Call Traces (MJS, XZ), pp. 221–230.
ISMM-2009-SerranoZ #garbage collection #optimisation #using
Placement optimization using data context collected during garbage collection (MJS, XZ), pp. 69–78.
CGO-2008-ZhuangKSC #analysis #difference #framework #named #performance #virtual machine
Perfdiff: a framework for performance difference analysis in a virtual machine environment (XZ, SK, MJS, JDC), pp. 4–13.
CGO-2006-ZhangZP #compilation #optimisation #security
Compiler Optimizations to Reduce Security Overhead (TZ, XZ, SP), pp. 346–357.
LCTES-2006-ZhuangP #analysis #compilation #concurrent #effectiveness #network #thread
Effective thread management on network processors with compiler analysis (XZ, SP), pp. 72–82.
PLDI-2006-ZhuangSCC #adaptation #performance #profiling
Accurate, efficient, and adaptive calling context profiling (XZ, MJS, HWC, JDC), pp. 263–271.
CGO-2005-ZhangZP
Building Intrusion-Tolerant Secure Software (TZ, XZ, SP), pp. 255–266.
PLDI-2005-ZhuangP #difference
Differential register allocation (XZ, SP), pp. 168–179.
ASPLOS-2004-ZhuangZP #framework #information management #named
HIDE: an infrastructure for efficiently protecting information leakage on the address bus (XZ, TZ, SP), pp. 72–84.
LCTES-2004-ZhuangP #embedded #power management
Power-efficient prefetching via bit-differential offset assignment on embedded processors (XZ, SP), pp. 67–77.
LCTES-2004-ZhuangZP #embedded
Hardware-managed register allocation for embedded processors (XZ, TZ, SP), pp. 192–201.
PLDI-2004-ZhuangP #network #parallel #thread
Balancing register allocation across threads for a multithreaded network processor (XZ, SP), pp. 289–300.
LCTES-2003-ZhuangLP #embedded #optimisation
Storage assignment optimizations through variable coalescence for embedded processors (XZ, CL, SP), pp. 220–231.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.