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Travelled to:
1 × USA
Collaborated with:
∅
Talks about:
hierarch (1) circuit (1) verif (1)

Person: Yiwan Wong

DBLP DBLP: Wong:Yiwan

Contributed to:

DAC 19851985

Wrote 1 papers:

DAC-1985-Wong #verification
Hierarchical circuit verification (YW), pp. 695–701.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.