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Used together with:
vhdl (1)
simul (1)
semant (1)
state (1)
interoper (1)

Stem abstact$ (all stems)

1 papers:

DATEDATE-1999-Sasaki #semantics #simulation #state machine
A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine (HS), p. 353–?.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.