BibSLEIGH — A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine

Hisashi Sasaki
A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine
DATE, 1999.

DATE 1999

@inproceedings{DATE-1999-Sasaki,
	author        = "Hisashi Sasaki",
	booktitle     = "{Proceedings of the Fourth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.1999.761145",
	isbn          = "0-7695-0078-1",
	pages         = "353--None",
	publisher     = "{IEEE Computer Society}",
	title         = "{A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine}",
	year          = 1999,
}

Hisashi SasakiA Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State MachineDATE, 1999.

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Hisashi Sasaki
A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine
DATE, 1999.