3 papers:
DAC-2013-MinJP #energy #named #optimisation #reduction- XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs (SMM, HJ, SP), p. 10.
DATE-2013-MartinB #configuration management #integration- Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples (FM, PB), p. 169.
- DAC-2008-KwonYHMCE #approach #memory management #parallel
- A practical approach of memory access parallelization to exploit multiple off-chip DDR memories (WCK, SY, SMH, BM, KMC, SKE), pp. 447–452.
