Stem dram$ (all stems)

77 papers:

DAC-2015-PengKPPJCL #3d #architecture #design #policy

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM (YP, BWK, YSP, KIP, SJJ, JSC, SKL), p. 6.

DAC-2015-WangHWLL #assembly #memory management #named

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory (YW, YH, CW, HL, XL), p. 6.

DATE-2015-GomonyGAAG #memory management #realtime #scalability

A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems (MDG, JG, BA, NCA, KGWG), pp. 193–198.

DATE-2015-HashemianSWWCP #array #authentication #robust #using

A robust authentication methodology using physically unclonable functions in DRAM arrays (MSH, BPS, FGW, DJW, SC, CAP), pp. 647–652.

DATE-2015-SchaffnerGSB #architecture #image #linear

DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS (MS, FKG, AS, LB), pp. 707–712.

DATE-2015-Weis0ESVGKW #fault #metric #modelling

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs (CW, MJ, PE, CS, PV, SG, MK, NW), pp. 495–500.

DATE-2015-YinLLWG15a #policy

Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache (SY, JL, LL, SW, YG), pp. 187–192.

DATE-2015-ZhangZCY #scalability

Exploiting DRAM restore time variations in deep sub-micron scaling (XZ, YZ, BRC, JY), pp. 477–482.

SAC-2015-LeeKKE #algorithm #architecture #hybrid #memory management #named

M-CLOCK: migration-optimized page replacement algorithm for hybrid DRAM and PCM memory architecture (ML, DK, JK, YIE), pp. 2001–2006.

HPCA-2015-FarahaniAMK #architecture #memory management #named #standard

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (AFF, JHA, KM, NSK), pp. 283–295.

HPCA-2015-LeeKPKSCM #adaptation #optimisation

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case (DL, YK, GP, SMK, VS, KKWC, OM), pp. 489–501.

HPCA-2015-SonLSKKA #architecture #named

CiDRA: A cache-inspired DRAM resilience architecture (YHS, SL, OS, SK, NSK, JHA), pp. 502–513.

DAC-2014-HameedBH #architecture #latency #novel

Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture (FH, LB, JH), p. 6.

DATE-2014-0001GWKAWG #optimisation #performance #runtime

Exploiting expendable process-margins in DRAMs for run-time performance optimization (KC, SG, CW, MK, BA, NW, KG), pp. 1–6.

DATE-2014-BeneventiBVDB #analysis #identification #logic

Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip (FB, AB, PV, DD, LB), pp. 1–4.

DATE-2014-GomonyAG #optimisation #performance #realtime

Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems (MDG, BA, KG), pp. 1–6.

DATE-2014-JaksicC #energy #how #protocol

DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy (ZJ, RC), pp. 1–4.

DATE-2014-PrenatPLGJDSPN #logic #power management

Magnetic memories: From DRAM replacement to ultra low power logic chips (GP, GdP, CL, OG, KJ, BD, RCS, ILP, JPN), p. 1.

DATE-2014-Sadri0WWB #3d #energy #optimisation #using

Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh (MS, MJ, CW, NW, LB), pp. 1–4.

HPCA-2014-ChangLCAWKM #performance

Improving DRAM performance by parallelizing refreshes with accesses (KKWC, DL, ZC, ARA, CW, YK, OM), pp. 356–367.

HPCA-2014-ZhangPXSX #architecture #memory management #named

CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture (TZ, MP, CX, GS, YX), pp. 368–379.

HPDC-2014-MittalVL #embedded #energy #performance

Improving energy efficiency of embedded DRAM caches for high-end computing systems (SM, JSV, DL), pp. 99–110.

DAC-2013-0001WAWG #approach #empirical #estimation #towards

Towards variation-aware system-level power estimation of DRAMs: an empirical approach (KC, CW, BA, NW, KG), p. 8.

DAC-2013-MinJP #energy #named #optimisation #reduction

XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs (SMM, HJ, SP), p. 10.

DATE-2013-0001WAWG #3d #energy #modelling

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs (KC, CW, BA, NW, KG), pp. 236–241.

DATE-2013-El-NacouziAPZJM #detection #scalability

A dual grain hit-miss detector for large die-stacked DRAM caches (MEN, IA, MP, JZ, NDEJ, AM), pp. 89–92.

DATE-2013-GuoYZC #hybrid #low cost

Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer (JG, JY, YZ, YC), pp. 859–864.

DATE-2013-HameedBH #adaptation #multi

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores (FH, LB, JH), pp. 77–82.

DATE-2013-NoguchiNAFAKNMN #energy #hybrid #memory management #performance

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory (HN, KN, KA, SF, EA, KK, TN, SM, HN), pp. 1813–1818.

ICEIS-v1-2013-TuW #industrial #migration

Technology Migration Determination Model for DRAM Industry (YMT, CIW), pp. 389–394.

HPCA-2013-LeeKH0 #power management

Skinflint DRAM system: Minimizing DRAM chip writes for low power (YL, SK, SH, JL), pp. 25–34.

HPCA-2013-LeeKSLSM #architecture #latency #low cost

Tiered-latency DRAM: A low latency and low cost DRAM architecture (DL, YK, VS, JL, LS, OM), pp. 615–626.

HPCA-2013-NairCQ #memory management

A case for Refresh Pausing in DRAM memory systems (PJN, CCC, MKQ), pp. 627–638.

DAC-2012-HuangYCL #case study #industrial

Alternate hammering test for application-specific DRAMs and an industrial case study (RFH, HYY, MCTC, SCL), pp. 1012–1017.

DAC-2012-KimLCKWYL #cpu #gpu #hybrid #in memory #memory management

Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU (DK, SL, JC, DK, DHW, SY, SL), pp. 888–896.

DAC-2012-MengKC #3d #constraints #energy #manycore #optimisation #performance

Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints (JM, KK, AKC), pp. 648–655.

DAC-2012-ZhangWCHL #fine-grained #multi #performance

Heterogeneous multi-channel: fine-grained DRAM control for both system performance and power efficiency (GZ, HW, XC, SH, PL), pp. 876–881.

DATE-2012-ChenLMABJ #3d #architecture #in memory #memory management #modelling #named

CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory (KC, SL, NM, JHA, JBB, NPJ), pp. 33–38.

DATE-2012-GomonyWAWG #mobile #realtime

DRAM selection and configuration for real-time mobile systems (MDG, CW, BA, NW, KG), pp. 51–56.

DATE-2012-MengC #3d #analysis #energy #performance #runtime

Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency (JM, AKC), pp. 611–616.

DATE-2012-WeisLBW #3d #energy #performance

An energy efficient DRAM subsystem for 3D integrated SoCs (CW, IL, LB, NW), pp. 1138–1141.

ASPLOS-2012-HwangSS #comprehension #design #fault

Cosmic rays don’t strike twice: understanding the nature of DRAM errors and the implications for system design (AAH, IAS, BS), pp. 111–122.

HPCA-2012-ChatterjeeMBDJ #staged

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads (NC, NM, RB, AD, NPJ), pp. 41–52.

HPCA-2012-JeongYSSLE #locality #memory management #parallel

Balancing DRAM locality and parallelism in shared memory CMP systems (MKJ, DHY, DS, MS, IL, ME), pp. 53–64.

DAC-2011-AadithyaVDR #impact analysis #named #predict #probability #random

MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMs (KVA, SV, AD, JSR), pp. 292–297.

DAC-2011-LiuZXL #clustering #hybrid #in memory #memory management #power management

Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory (TL, YZ, CJX, ML), pp. 405–410.

DAC-2011-ParkYL #hybrid #in memory #memory management #power management

Power management of hybrid DRAM/PRAM-based main memory (HP, SY, SL), pp. 59–64.

DATE-2011-WeisWLB #3d #design

Design space exploration for 3D-stacked DRAMs (CW, NW, IL, LB), pp. 389–394.

SAC-2011-SeokPP #algorithm #hybrid #in memory #memory management #migration

Migration based page caching algorithm for a hybrid main memory of DRAM and PRAM (HS, YP, KHP), pp. 595–599.

ASPLOS-2011-LiuPMZ #clustering #named

Flikker: saving DRAM refresh-power through critical data partitioning (SL, KP, TM, BGZ), pp. 213–224.

HPCA-2011-LiuLNMMH #hardware

Hardware/software techniques for DRAM thermal management (SL, BL, AN, SOM, GM, NH), pp. 515–525.

DATE-2010-LoiB #3d #distributed #framework #interface #manycore #memory management #performance

An efficient distributed memory interface for many-core platform with 3D stacked DRAM (IL, LB), pp. 99–104.

ASPLOS-2010-SudanCNABD #named #performance

Micro-pages: increasing DRAM efficiency with locality-aware data placement (KS, NC, DWN, MA, RB, AD), pp. 219–230.

HPCA-2010-BiDG #energy

Delay-Hiding energy management mechanisms for DRAM (MB, RD, CG), pp. 1–10.

HPCA-2010-JiangMZUIMNSB #adaptation #named

CHOP: Adaptive filter-based DRAM caching for CMP server platforms (XJ, NM, LZ, MU, RI, SM, DN, YS, RB), pp. 1–12.

DAC-2009-ChaoYHLC #fault #metaprogramming #modelling

Fault models for embedded-DRAM macros (MCTC, HYY, RFH, SCL, CYC), pp. 714–719.

DAC-2009-DhimanAR #hybrid #in memory #memory management #named

PDRAM: a hybrid PRAM and DRAM main memory system (GD, RZA, TR), pp. 664–469.

DATE-2009-FacchiniCVPCDBM #3d #evaluation #mobile #performance

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications (MF, TC, AV, MP, FC, WD, LB, PM), pp. 923–928.

DATE-2009-VignonCDMF #3d #architecture #novel

A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context (AV, SC, WD, PM, MF), pp. 929–933.

DAC-2008-LiuMZM #architecture

A power and temperature aware DRAM architecture (SL, SOM, YZ, GM), pp. 878–883.

DATE-2008-VersenSSD #analysis #locality

Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices (MV, AS, JS, DD), pp. 776–779.

HPCA-2008-AggarwalCLS #power management

Power-Efficient DRAM Speculation (NA, JFC, MHL, JES), pp. 317–328.

HPCA-2008-HurL #approach #power management

A comprehensive approach to DRAM power management (IH, CL), pp. 305–316.

DATE-2006-Al-ArsHG #fault #modelling #testing

Space of DRAM fault models and corresponding testing (ZAA, SH, AJvdG), pp. 1252–1257.

HPCA-2006-VenkatesanHR #agile

Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM (RKV, SH, ER), pp. 155–165.

DATE-2005-Al-ArsHMG #analysis #fault #framework #generative #testing

Framework for Fault Analysis and Test Generation in DRAMs (ZAA, SH, GM, AJvdG), pp. 1020–1021.

HPCA-2005-ZhuZ #comparison #memory management #optimisation #performance #smt

A Performance Comparison of DRAM Memory System Optimizations for SMT Processors (ZZ, ZZ), pp. 213–224.

DAC-2003-ChoiK #design #embedded #layout #memory management #performance

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design (YC, TK), pp. 881–886.

DATE-2003-Al-ArsGBR #fault #optimisation #simulation #testing #using

Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation (ZAA, AJvdG, JB, DR), pp. 10484–10489.

DAC-2002-DelaluzSKVI #energy

Scheduler-based DRAM energy management (VD, AS, MTK, NV, MJI), pp. 697–702.

DATE-2001-Al-ArsG #array #behaviour #embedded #memory management

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs (ZAA, AJvdG), pp. 496–503.

HPCA-2001-DelaluzKVSI #energy #hardware #using

DRAM Energy Management Using Software and Hardware Directed Power Mode Control (VD, MTK, NV, AS, MJI), pp. 159–169.

HPCA-2001-LinRB #design #memory management

Reducing DRAM Latencies with an Integrated Memory Hierarchy Design (WFL, SKR, DB), pp. 301–312.

DATE-1999-GoorN #evaluation #industrial #testing

Industrial Evaluation of DRAM Tests (AJvdG, JdN), pp. 623–630.

HPCA-1999-InoueKM #logic #memory management

Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs (KI, KK, KM), pp. 218–222.

DATE-1998-WehnH #architecture #embedded #trade-off

Embedded DRAM Architectural Trade-Offs (NW, SH), pp. 704–708.

ICPR-1996-YamashitaFO #array #interface #memory management #realtime

An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications (NY, YF, SO), pp. 575–580.