BibSLEIGH corpus
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Used together with:
rout (6)
router (5)
channel (3)
cell (3)
layer (3)

Stem gridless$ (all stems)

12 papers:

Gridless pin access in detailed routing (TN), pp. 170–175.
DACDAC-2010-LinL #graph
Double patterning lithography aware gridless detailed routing with innovative conflict graph (YHL, YLL), pp. 398–403.
DACDAC-2006-ChenCCCH #novel
Novel full-chip gridless routing considering double-via insertion (HYC, MFC, YWC, LC, BH), pp. 755–760.
DATEEDTC-1997-TsengS #multi #standard #using
A gridless multi-layer router for standard cell circuits using CTM cells (HPT, CS), pp. 319–326.
DACDAC-1990-GidwaniS #named
MISER: An Integrated Three Layer Gridless Channel Router and Compactor (RAG, NAS), pp. 698–703.
DACDAC-1990-SatoKO #hardware #implementation #memory management
A Hardware Implementation of Gridless Routing Based on Content Addressable Memory (MS, KK, TO), pp. 646–649.
DACDAC-1990-SchieleKJK #design #industrial
A Gridless Router for Industrial Design Rules (WLS, TK, KMJ, FHK), pp. 626–631.
Via Minimization for Gridless Layouts (NJN, SM, KN), pp. 159–165.
DACDAC-1987-Ng #design
A “gridless” Variable-Width Channel Router for Marco Cell Design (CHN), pp. 633–636.
A Three-Layer Gridless Channel Router with Compaction (DBP), pp. 146–151.
A method for gridless routing of printed circuit boards (ACF, KJM, GJB, GS), pp. 509–515.
DACDAC-1980-Lauther #data type
A data structure for gridless routing (UL), pp. 603–609.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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