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Used together with:
layout (3)
rout (2)
integr (2)
placement (2)
cmos (2)

Stem polycel$ (all stems)

7 papers:

DACDAC-1986-Gerveshi #comparison #logic
Comparison of CMOS PLA and polycell representations of control logic (CMG), pp. 638–642.
DACDAC-1982-KambeCKION #algorithm #evaluation
A placement algorithm for polycell LSI and ITS evaluation (TK, TC, SK, TI, NO, IN), pp. 655–662.
DACDAC-1981-LeeCJ #automation #generative
Automatic generation and characterization of CMOS polycells (CML, BRC, SJ), pp. 220–224.
DACDAC-1981-MartinBLMMTW #design #named #problem
CELTIC — solving the problems of LSI design with an integrated polycell DA system (GM, JB, TL, DM, JM, DT, LW), pp. 804–811.
The minimum width routing of A 2-row 2-layer polycell-layout (TK, YK), pp. 290–296.
DACDAC-1976-Persky #automation #layout #named #string
PRO — an automatic string placement program for polycell layout (GP), pp. 417–424.
DACDAC-1973-KernighanSP #algorithm
An optimum channel-routing algorithm for polycell layouts of integrated circuits (BWK, DGS, GP), pp. 50–59.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.