Stem cmos$ (all stems)

211 papers:

DATE-2015-AhmadyanGNCV #analysis #diagrams #performance

Fast eye diagram analysis for high-speed CMOS circuits (SNA, CG, SN, EC, SV), pp. 1377–1382.

DATE-2015-CilingirogluZUK #representation

Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits (TBC, MZ, AU, WCK, JK, AJ, BBG, MSÜ), pp. 597–600.

DATE-2015-DghaisR #empirical #modelling #simulation

Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation (WD, JR), pp. 1555–1558.

DATE-2015-GarciaMSN #multi #performance

High performance single supply CMOS inverter level up shifter for multi: supply voltages domains (JCG, JAMN, JS, SN), pp. 1273–1276.

DATE-2015-LuLJLHCL #standard

Simultaneous transistor pairing and placement for CMOS standard cells (AL, HJL, EJJ, YPL, CHH, CCC, RBL), pp. 1647–1652.

DATE-2015-SchaffnerGSB #architecture #image #linear

DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS (MS, FKG, AS, LB), pp. 707–712.

DATE-2015-SporrerBVMRMBBP #array #smarttech

Integrated CMOS receiver for wearable coil arrays in MRI applications (BS, LB, CV, AM, JR, JM, DOB, TB, KPP, GT, QH), pp. 1689–1694.

DAC-2014-KabirS #hybrid

Computing with Hybrid CMOS/STO Circuits (MK, MRS), p. 6.

DATE-2014-BhargavaM #encryption #generative #performance #reliability

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS (MB, KM), pp. 1–6.

DATE-2014-Huang #performance

A high performance SEU-tolerant latch for nanoscale CMOS technology (ZH), pp. 1–5.

DATE-2014-Kreupl

Advancing CMOS with carbon electronics (FK), pp. 1–6.

DATE-2014-NarayananDCCLW #using #video

Video analytics using beyond CMOS devices (VN, SD, GC, DMC, SPL, PW), pp. 1–5.

DAC-2013-FariborziCNCHLLS

Relays do not leak: CMOS does (HF, FC, RN, IRC, LH, RL, TJKL, VS), p. 4.

DATE-2013-ChangWB #design

Process-variation-aware Iddq diagnosis for nano-scale CMOS designs — the first step (CLC, CHPW, JB), pp. 454–457.

DATE-2013-De #design

Near-threshold voltage design in nanoscale CMOS (VD), p. 612.

DATE-2013-GielenM #modelling #probability #simulation

Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS (GGEG, EM), pp. 326–331.

DATE-2013-MishraBTRF #energy #power management

A sub-μa power management circuit in 0.18μm CMOS for energy harvesters (BM, CB, GT, CR, PAF), pp. 1197–1202.

DATE-2013-ParkQPC #embedded #logic #self

40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS (SP, MQ, LSP, APC), pp. 1637–1642.

DATE-2013-RethyDSDG #interface #network #power management

A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks (JVR, HD, VDS, WD, GGEG), pp. 1431–1435.

DAC-2012-RoaCJ #logic

Material implication in CMOS: a new kind of logic (ER, WHC, BJ), pp. 1258–1259.

DATE-2012-BiZLCP #design

Spintronic memristor based temperature sensor design with CMOS current reference (XB, CZ, HL, YC, REP), pp. 1301–1306.

DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability

Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.

DATE-2012-PanagopoulosAR #approach #framework #hybrid #simulation

A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach (GP, CA, KR), pp. 1443–1446.

DATE-2012-TorresAGPR #benchmark #metric

Beyond CMOS — benchmarking for future technologies (CMST, JA, MWMG, RMP, WR), pp. 129–134.

DAC-2011-ChangC #3d #array #image #metric #performance #quality #specification

Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers (HMC, KT(C), pp. 759–764.

DAC-2011-FuketaIYTNSS #logic

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates (HF, SI, TY, MT, MN, HS, TS), pp. 984–989.

DAC-2011-KrishnamurthyMS #encryption #energy

High-performance energy-efficient encryption in the sub-45nm CMOS Era (RK, SM, FS), p. 332.

DAC-2011-SaripalliMDN #energy #hybrid

An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores (VS, AKM, SD, VN), pp. 729–734.

DAC-2011-SternRVRCPFR

CMOS compatible nanowires for biosensing (ES, DAR, AV, NKR, JMC, JP, TMF, MR), pp. 718–722.

DATE-2011-GielenMW #analysis #reliability

Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation (GGEG, EM, PHNDW), pp. 1474–1479.

DATE-2011-LopezMBPGE #design #interface #process #programmable

Systematic design of a programmable low-noise CMOS neural interface for cell activity recording (CML, SM, CB, RP, GGEG, WE), pp. 818–823.

DAC-2010-ChangHKCW #3d #fault

An error tolerance scheme for 3D CMOS imagers (HMC, JLH, DMK, KT(C, CWW), pp. 917–922.

DATE-2010-AlordaTBS #power management

Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs (BA, GT, SAB, JS), pp. 429–434.

DATE-2010-ChironiDBCI

A compact digital amplitude modulator in 90nm CMOS (VC, BD, AB, JC, MI), pp. 702–705.

DATE-2010-FanucciPDSTCLT #programmable

An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability (LF, GP, PD, RS, FT, PC, LL, PT), pp. 526–531.

DATE-2010-GaoH #geometry #optimisation #programming #using

A power optimization method for CMOS Op-Amps using sub-space based geometric programming (WG, RH), pp. 508–513.

DATE-2010-GeisNRRVC

An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation (AG, PN, JR, YR, GV, JC), pp. 697–701.

DATE-2010-HenryN #power management

From transistors to MEMS: Throughput-aware power gating in CMOS circuits (MBH, LN), pp. 130–135.

DATE-2010-HuangFLYSSC #design #flexibility #named #novel #pseudo

Pseudo-CMOS: A novel design style for flexible electronics (TCH, KF, CML, YHY, TS, TS, KTC), pp. 154–159.

DAC-2009-Borkar #design

Design perspectives on 22nm CMOS and beyond (SB), pp. 93–94.

DAC-2009-Kuhn #challenge #scalability

CMOS scaling beyond 32nm: challenges and opportunities (KJK), pp. 310–313.

DATE-2009-SathanurPBMM #clustering #design #variability

Physically clustered forward body biasing for variability compensation in nanometer CMOS design (AVS, AP, LB, GDM, EM), pp. 154–159.

DAC-2008-ChengLLCC #image #named #visual notation

iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor (CCC, CHL, CTL, SCC, LGC), pp. 90–95.

DAC-2008-ReddyPL #detection #on the #testing

On tests to detect via opens in digital CMOS circuits (SMR, IP, CL), pp. 840–845.

DATE-2008-AmelifardHFP #logic #multi #stack

A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect (BA, SH, HF, MP), pp. 568–573.

DATE-2008-BadarogluDLC #using

Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment (MB, GD, FL, OC), pp. 873–878.

DATE-2008-GielenWMLMKGRN #challenge #reliability

Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies (GGEG, PHNDW, EM, JL, JMM, BK, GG, RR, MN), pp. 1322–1327.

DATE-2008-Mitra #challenge #reliability #robust

Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges (SM), pp. 941–946.

DATE-2008-Schat #clustering #fault #process

Fault Clustering in deep-submicron CMOS Processes (JS), pp. 511–514.

DATE-2008-SreedharSK #fault #modelling #on the #testing

On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits (AS, AS, SK), pp. 616–621.

DAC-2007-AgarwalN #process

Characterizing Process Variation in Nanometer CMOS (KA, SRN), pp. 396–399.

DAC-2007-DadgourB #analysis #design #hybrid #power management

Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications (HFD, KB), pp. 306–311.

DAC-2007-RastogiCK #on the

On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method (AR, WC, SK), pp. 712–715.

DAC-2007-ZhangSJ #architecture #configuration management #design #hybrid #named #optimisation

NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture (WZ, LS, NKJ), pp. 300–305.

DAC-2006-AminKMKC #library #multi

A multi-port current source model for multiple-input switching effects in CMOS library cells (CSA, CVK, NM, KK, EC), pp. 247–252.

DAC-2006-AnanthanR #physics #process

A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS (HA, KR), pp. 413–418.

DAC-2006-Borkar

Electronics beyond nano-scale CMOS (SB), pp. 807–808.

DAC-2006-NieuwoudtRM #named #optimisation #synthesis

SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers (AN, TR, YM), pp. 879–884.

DAC-2006-NuzzoPBPGT

A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW (PN, GVdP, FDB, LVdP, BG, PT), pp. 873–878.

DAC-2006-PanCHCLCLLHWLLTYMCCPHCH #ram

A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications (JSP, HCC, BYH, HCC, RL, CHC, YCL, CL, LH, CLW, MHL, CYL, SNT, JNY, CPM, YC, SHC, HCP, PCH, BC, AH), pp. 290–291.

DAC-2006-RadT #clustering #hybrid

A new hybrid FPGA with nanoscale clusters and CMOS routing (RMR, MT), pp. 727–730.

DAC-2006-ZhangJS #architecture #configuration management #hybrid #named

NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture (WZ, NKJ, LS), pp. 711–716.

DATE-2006-ChakrapaniACKPS #architecture #embedded #probability

Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology (LNC, BESA, SC, PK, KVP, BS), pp. 1110–1115.

DATE-2006-GarciaMN

Bootstrapped full--swing CMOS driver for low supply voltage operation (JCG, JAMN, SN), pp. 410–411.

DATE-2006-MoezE #distributed #process

A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process (KKM, MIE), pp. 405–409.

DATE-2006-NiclassSC #array

A single photon avalanche diode array fabricated in deep-submicron CMOS technology (CN, MS, EC), pp. 81–86.

DATE-2006-SridharanC #modelling #multi #using

Modeling multiple input switching of CMOS gates in DSM technology using HDMR (JS, TC), pp. 626–631.

DATE-2006-YavariSR #design #hybrid

Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation (MY, OS, ÁRV), pp. 144–149.

DATE-DF-2006-BarontiDKMRSSSV

FlexRay transceiver in a 0.35 µm CMOS high-voltage technology (FB, PD, MK, RM, RR, RS, MS, RS, VV), pp. 201–205.

DAC-2005-GaoH #multi #reduction

Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages (FG, JPH), pp. 31–36.

DAC-2005-NatarajanKH

A 24 GHz phased-array transmitter in 0.18µm CMOS (AN, AK, AH), pp. 551–552.

DAC-2005-TiriHHLYSV #embedded #encryption

A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing (KT, DDH, AH, BCL, SY, PS, IV), pp. 222–227.

DATE-2005-GielenDCDJMV #design #question

Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? (GGEG, WD, PC, DD, EJ, KM, TV), pp. 36–42.

DATE-2005-KeezerGMT #low cost #multi #using

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL (DCK, CG, AMM, NT), pp. 152–157.

DATE-2005-KirsteinLZVVSLH

Cantilever-Based Biosensors in CMOS Technology (KUK, YL, MZ, CV, TV, WHS, JL, AH), pp. 1340–1341.

DATE-2005-KitaharaKMSF #design #multi #power management #reduction

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction (TK, NK, FM, KS, TF), pp. 646–647.

DATE-2005-MukhopadhyayBR #analysis #logic #modelling

Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits (SM, SB, KR), pp. 224–229.

DATE-2005-ThewesPSHFBAJESAHBHH #array

CMOS-Based Biosensor Arrays (RT, CP, MS, FH, AF, RB, MA, MJ, BE, PSB, MA, BH, GB, TH, HCH), pp. 1222–1223.

DATE-2005-VerleMAMA #optimisation #power management #protocol

Low Power Oriented CMOS Circuit Optimization Protocol (AV, XM, NA, PM, DA), pp. 640–645.

DATE-2005-ZuberWOSH #optimisation #power management #reduction

Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization (PZ, AW, RMBdO, WS, AH), pp. 986–987.

DAC-2004-DingM #logic #novel

A novel technique to improve noise immunity of CMOS dynamic logic circuits (LD, PM), pp. 900–903.

DAC-2004-KanjLAR

Noise characterization of static CMOS gates (RK, TL, BA, ER), pp. 888–893.

DATE-DF-2004-ChenYSMGH #design #using

Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology (YC, XY, DS, JM, JG, DLH), pp. 22–27.

DATE-DF-2004-Tissafi-DrissiOG #automation #design #framework #multi #named #performance

RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends (FTD, IO, FG), pp. 16–21.

DATE-v1-2004-GarciaMSN #scalability

A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit (JCG, JAMN, JS, HN), pp. 680–681.

DATE-v1-2004-RolindezMPB #generative #implementation

A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns (LR, SM, GP, AB), pp. 706–707.

DATE-v2-2004-GuilleyHMPP #hardware

CMOS Structures Suitable for Secured Hardware (SG, PH, YM, RP, JP), pp. 1414–1415.

DATE-v2-2004-RosselloS

A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk (JLR, JS), pp. 954–961.

DATE-2005-AndersenBTBBHM04 #pipes and filters

A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS (TNA, AB, FT, JB, TEB, BH, ØM), pp. 219–222.

DATE-2005-KirsteinSSHVH04 #monitoring

A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring (KUK, JS, TS, CH, TV, AH), pp. 210–214.

DATE-2005-SandnerCSHK04 #power management

A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS (CS, MC, AS, TH, FK), pp. 223–226.

DAC-2003-MukhopadhyayRR #estimation #logic #modelling

Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling (SM, AR, KR), pp. 169–174.

DAC-2003-SengerMMGKGB

A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference (RMS, EDM, MSM, FHG, KLK, MRG, RBB), pp. 520–525.

DATE-2003-IskanderDAMHSM #synthesis #using

Synthesis of CMOS Analog Cells Using AMIGO (RI, MD, MA, MM, NH, NS, SM), pp. 20297–20302.

DATE-2003-SirisantanaR #logic #power management

Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies (NS, KR), pp. 11160–11161.

DAC-2002-BadarogluTDWMVG #optimisation #reduction #using

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.

DAC-2002-IonescuDMBG #hybrid #towards

Few electron devices: towards hybrid CMOS-SET integrated circuits (AMI, MJD, SM, KB, JG), pp. 88–93.

DAC-2002-SeryBD #question #why

Life is CMOS: why chase the life after? (GS, SB, VD), pp. 78–83.

DAC-2002-SteyaertV #named #paradigm #power management #question

CMOS: a paradigm for low power wireless? (MS, PJV), pp. 836–841.

DATE-2002-BeroulleBLN #on the

On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems (VB, YB, LL, PN), p. 1120.

DATE-2002-DingM #performance

Optimal Transistor Tapering for High-Speed CMOS Circuits (LD, PM), pp. 708–713.

DATE-2002-KumarMB #embedded #testing

IDDT Testing of Embedded CMOS SRAMs (SAK, RZM, DMB), p. 1117.

DATE-2002-MartinezAQSK #encoding #implementation #power management

An Encoding Technique for Low Power CMOS Implementations of Controllers (MM, MJA, JMQ, HS, MK), p. 1083.

DAC-2001-GorenSW #analysis #novel #pipes and filters #probability

A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC (DG, ES, IAW), pp. 127–132.

DAC-2001-RaahemifarA #detection #fault

Fault Characterizations and Design-for-Testability Technique for Detecting IDDQ Faults in CMOS/BiCMOS Circuits (KR, MA), pp. 313–316.

DATE-2001-CappuccinoC #performance

CMOS sizing rule for high performance long interconnects (GC, GC), p. 817.

DATE-2001-HashizumeIYT #detection #fault

CMOS open defect detection by supply current test (MH, MI, HY, TT), p. 509.

DATE-2001-NaiduJ #power management

Minimizing stand-by leakage power in static CMOS circuits (SRN, ETAFJ), pp. 370–376.

DATE-2001-RioRMPR #design #top-down

Top-down design of a xDSL 14-bit 4MS/s sigma-delta modulator in digital CMOS technology (RdR, JLdlR, FM, MBPV, ÁRV), pp. 348–352.

DATE-2001-WernerGWR

Crosstalk noise in future digital CMOS circuits (CW, RG, AW, UR), pp. 331–335.

DAC-2000-PlasVDBGS #design

Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter (GVdP, JV, WD, AvdB, GGEG, WMCS), pp. 452–457.

DATE-2000-YangC #logic #synthesis

Synthesis for Mixed CMOS/PTl Logic (CY, MJC), p. 750.

DAC-1999-AllenBS

Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology (DA, DB, BS), pp. 892–897.

DAC-1999-ChuangP #design #perspective

SOI Digital CMOS VLSI — a Design Perspective (CTC, RP), pp. 709–714.

DAC-1999-Eaglesham

0.18m CMOS and Beyond (DJE), pp. 703–708.

DAC-1999-JohnsonSR #performance

Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS (MCJ, DS, KR), pp. 442–445.

DAC-1999-LiTRK #modelling #simulation

Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation (TL, CHT, ER, SMK), pp. 549–554.

DAC-1999-SundararajanP #power management #synthesis #using

Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages (VS, KKP), pp. 72–75.

DAC-1999-WeiCRYD #design #power management

Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications (LW, ZC, KR, YY, VD), pp. 430–435.

DATE-1999-LatorreBHPN #design #modelling

Design, Characterization & Modelling of a CMOS Magnetic Field Sensor (LL, YB, PH, FP, PN), pp. 239–243.

DATE-1999-LauwersG #estimation #performance

A Power Estimation Model for High-Speed CMOS A/D Converters (EL, GGEG), pp. 401–405.

DATE-1999-Nunez-AldanaV #effectiveness #performance #synthesis

An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis (ANA, RV), pp. 406–411.

DATE-1999-PedramW #design

Battery-Powered Digital CMOS Design (MP, QW), pp. 72–76.

DATE-1999-SchwenckerEGA #automation #constraints

Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints (RS, JE, HEG, KA), pp. 323–327.

DATE-1999-StopjakovaMS #monitoring #testing

On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC (VS, HARM, MS), pp. 538–542.

DAC-1998-KwakP #estimation #fault #logic #statistics

An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits (BK, ESP), pp. 690–693.

DAC-1998-LiK #layout #verification

Layout Extraction and Verification Methodology CMOS I/O Circuits (TL, SMK), pp. 291–296.

DAC-1998-NassifDH #modelling #robust #verification

Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (NN, MPD, DHH), pp. 230–235.

DAC-1998-RaelRA #design

Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver (JR, AR, AAA), pp. 44–49.

DAC-1998-WeiCJRD #design #optimisation #performance

Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits (LW, ZC, MJ, KR, VD), pp. 489–494.

DATE-1998-BisdounisKGN #modelling

Switching Response Modeling of the CMOS Inverter for Sub-micron Devices (LB, OGK, CEG, SN), pp. 729–735.

DATE-1998-EckmuellerGG

Hierarchical Characterization of Analog Integrated CMOS Circuits (JE, MG, HEG), pp. 636–643.

DATE-1998-FassnachtS #analysis #optimisation

Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset (UF, JS), pp. 325–331.

DATE-1998-JiangC #approximate #estimation

Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits (YMJ, KTC), pp. 698–702.

DATE-1998-KoehlBLKP #design

A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset (JK, UB, TL, BK, TP), pp. 312–320.

DATE-1998-PullelaPDV

CMOS Combinational Circuit Sizing by Stage-wise Tapering (SP, RP, AD, GV), pp. 985–986.

DATE-1998-Rodriguez-MontanesF #estimation

Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs (RRM, JF), pp. 490–494.

DAC-1997-GrundmannDAR #design #performance #using

Designing High Performance CMOS Microprocessors Using Full Custom Techniques (WJG, DD, RLA, NLR), pp. 722–727.

DAC-1997-GuptaH #2d #generative #layout #named #optimisation

CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells (AG, JPH), pp. 452–455.

DAC-1997-KaoCA #multi

Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology (JK, AC, DA), pp. 409–414.

DAC-1997-KimK #algorithm #design #layout #performance

An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design (JK, SMK), pp. 456–459.

DAC-1997-KrsticC #generative

Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits (AK, KTC), pp. 383–388.

DAC-1997-PantDC #energy #logic #network #optimisation #power management #random

Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks (PP, VD, AC), pp. 403–408.

DAC-1997-WalterLDLMKW #approach #multi #random #simulation #verification

Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors (JAW, JL, GD, BL, HJM, KWK, BW), pp. 89–94.

EDTC-1997-GavrilovGRBJV #performance

Fast power loss calculation for digital static CMOS circuits (SG, AG, SR, DB, LGJ, GV), pp. 411–415.

EDTC-1997-KunduG #analysis

Inductance analysis of on-chip interconnects [deep submicron CMOS] (SK, UG), pp. 252–255.

EDTC-1997-LuS

A CMOS low-voltage, high-gain op-amp (GNL, GS), pp. 51–55.

EDTC-1997-ManichF #process

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model (SM, JF), pp. 597–602.

EDTC-1997-StopjakovaM #monitoring #testing

CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits (VS, HARM), pp. 266–270.

EDTC-1997-TurgisDPA #modelling

Internal power modelling and minimization in CMOS inverters (ST, JMD, JMP, DA), pp. 603–608.

DAC-1996-BoglioloBR #estimation

Power Estimation of Cell-Based CMOS Circuits (AB, LB, BR), pp. 433–438.

DAC-1996-ChengTDRK #named #reliability

iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips (YKC, CCT, AD, ER, SMK), pp. 548–551.

DAC-1996-KudvaGJN #multi #network #synthesis

Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes (PK, GG, HMJ, SMN), pp. 77–82.

DAC-1996-LimSPS #approach #estimation #process #statistics

A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits (YJL, KIS, HJP, MS), pp. 445–450.

DAC-1995-KonukFL #fault #network #performance #simulation

Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks (HK, FJF, TL), pp. 345–351.

DAC-1995-KruiskampL #algorithm #named #search-based #synthesis

DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm (WK, DL), pp. 433–438.

DAC-1994-DartuMQP #performance

A Gate-Delay Model for high-Speed CMOS Circuits (FD, NM, JQ, LTP), pp. 576–580.

DAC-1994-MehrotraFL #approach #optimisation #probability

Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits (SM, PDF, WL), pp. 36–40.

DAC-1994-SchobingerN #design #power management

Low Power CMOS Design Strategies (MS, TGN), pp. 594–595.

EDAC-1994-AbderrahmanKS #estimation

Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits (AA, BK, YS), p. 658.

EDAC-1994-AkitaA #logic #power management #probability

A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability (JA, KA), pp. 420–424.

EDAC-1994-ChessL #fault #generative

Generating Test Patterns for Bridge Faults in CMOS ICs (BC, TL), pp. 165–170.

EDAC-1994-FavalliDOR #fault #modelling

Modeling of Broken Connections Faults in CMOS ICs (MF, MD, PO, BR), pp. 159–164.

EDAC-1994-GevaertVNS

Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front End (DG, JV, JN, JS), pp. 75–79.

EDAC-1994-Rodriguez-MontanesF #analysis #fault #testing

Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability (RRM, JF), pp. 356–360.

EDAC-1994-Sachdev #logic #testing

Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing (MS), pp. 361–365.

EDAC-1994-XueDJ #analysis #fault #float #probability

Probability Analysis for CMOS Floating Gate Faults (HX, CD, JAGJ), pp. 443–448.

DAC-1993-CarlsonC #order #performance

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering (BSC, CYRC), pp. 361–366.

DAC-1993-ChessL #fault #simulation

Bridge Fault simulation strategies for CMOS integrated Circuits (BC, TL), pp. 458–462.

DAC-1993-KriplaniNYH #correlation

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits (HK, FNN, PY, INH), pp. 384–388.

DAC-1992-KriplaniNH #estimation

Maximum Current Estimation in CMOS Circuits (HK, FNN, INH), pp. 2–7.

DAC-1992-LeeNB #generative #named #testing

SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits (KJL, CN, MAB), pp. 26–29.

DAC-1991-HwangHLH #automation #generative #layout #performance

An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation (CYH, YCH, YLL, YCH), pp. 481–486.

DAC-1991-MaziaszH

Exact Width and Height Minimization of CMOS Cells (RLM, JPH), pp. 487–493.

DAC-1991-PanBGGY #design #verification

Timing Verification on a 1.2M-Device Full-Custom CMOS Design (JP, LLB, JG, WJG, YTY), pp. 551–554.

DAC-1990-Chakravarty #identification #on the

On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract) (SC), pp. 736–739.

DAC-1990-LeeH #automation #fault #generative #named #performance

SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits (HKL, DSH), pp. 660–666.

DAC-1989-Al-KhaliliZA #generative

A Module Generator for Optimized CMOS Buffers (AJAK, YZ, DAK), pp. 245–250.

DAC-1989-LeeHK #fault #generative #testing #using

Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits (HKL, DSH, KK), pp. 345–350.

DAC-1989-LueM

Extracting Schematic-like Information from CMOS Circuit Net-lists (WJL, LPM), pp. 690–693.

DAC-1989-RajsumanJM #detection #fault #using

CMOS Stuck-open Fault Detection Using Single Test Patterns (RR, APJ, YKM), pp. 714–717.

DAC-1989-WangKL #approach #fault #logic #robust #set

A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic Circuits (JFW, TYK, JYL), pp. 726–729.

DAC-1988-Boehner #automation #logic #named

LOGEX — an Automatic Logic Extractor Form Transistor to Gate Level for CMOS Technology (MB), pp. 517–522.

DAC-1988-BurchNYH #analysis #estimation #independence #reliability

Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits (RB, FNN, PY, DEH), pp. 294–299.

DAC-1988-Cherry #named

Pearl: A CMOS Timing Analyzer (JJC), pp. 148–153.

DAC-1988-ShiraishiSKTS #generative #logic

A High Packing Density Module Generator for CMOS Logic Cells (YS, JS, MK, AT, TS), pp. 439–444.

DAC-1988-StarkH #network #power management #using

Analyzing CMOS Power Supply Networks Using Ariel (DS, MH), pp. 460–464.

DAC-1987-Cirit

Transistor Sizing in CMOS Circuits (MAC), pp. 121–124.

DAC-1987-HofmannK #logic #optimisation

Delay Optimization of Combinational Static CMOS Logic (MH, JKK), pp. 125–132.

DAC-1987-Koeppe #fault #layout

Optimal Layout to Avoid CMOS Stuck-Open Faults (SK), pp. 829–835.

DAC-1987-MaiaszH #functional #layout #optimisation

Layout Optimization of CMOS Functional Cells (RLM, JPH), pp. 544–551.

DAC-1987-Serlet #combinator #performance

Fast, Small, and Static Combinatorial CMOS Circuits (BS), pp. 451–458.

DAC-1987-WuWN #automation #design #representation #rule-based #verification

A Rule-Based Circuit Representation for Automated CMOS Design and Verification (CFEW, ASW, LMN), pp. 786–792.

DAC-1986-Gerveshi #comparison #logic

Comparison of CMOS PLA and polycell representations of control logic (CMG), pp. 638–642.

DAC-1986-MarshburnLBCLC #assembly #named

DATAPATH: a CMOS data path silicon assembler (TM, IL, RB, DC, GL, PC), pp. 722–729.

DAC-1986-SaitoSYK #array #logic #rule-based #synthesis

A rule-based logic circuit synthesis system for CMOS gate arrays (TS, HS, MY, NK), pp. 594–600.

DAC-1986-ShihA #generative #physics #testing

Transistor-level test generation for physical failures in CMOS circuits (HCS, JAA), pp. 243–249.

DAC-1986-WeiweiX #algorithm #fault #generative #robust #testing

Robust test generation algorithm for stuck-open fault in CMOS circuits (WM, XL), pp. 236–242.

DAC-1985-Bergmann #design #independence

Generalised CMOS-a technology independent CMOS IC design style (NB), pp. 273–278.

DAC-1985-KaoFL #algorithm #automation

Algorithms for automatic transistor sizing in CMOS digital circuits (WHK, NF, CHL), pp. 781–784.

DAC-1985-NodaYFKKF #algorithm #array #automation #layout

Automatic layout algorithms for function blocks of CMOS gate arrays (SN, HY, EF, HK, HK, TF), pp. 46–52.

DAC-1984-ReddyAJ #detection #fault #logic

A gate level model for CMOS combinational logic circuits with application to fault detection (SMR, VDA, SKJ), pp. 504–509.

DAC-1984-TienTCCE #array #automation #layout #named

GALA — an automatic layout system for high density CMOS gate arrays (BNT, BST, JC, KSKC, SCE), pp. 657–662.

DAC-1983-Acken #fault #testing

Testing for bridging faults (shorts) in CMOS circuits (JMA), pp. 717–718.

DAC-1983-ChiangV #detection #fault #logic #network #on the

On fault detection in CMOS logic networks (KWC, ZGV), pp. 50–56.

DAC-1983-GriersonCRHKKMMN #array #collaboration #design #development

The UK5000 — successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test (JRG, BC, DR, REH, HK, JCK, JAM, JMM, CON), pp. 629–636.

DAC-1982-KangKL #adaptation #cpu #design #evolution #layout #logic #matrix #random

Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design (SMK, RHK, HFSL), pp. 170–174.

DAC-1981-El-Ziq #automation #fault #generative #testing

Automatic test generation for stuck-open faults in CMOS VLSI (YMEZ), pp. 347–354.

DAC-1981-LeeCJ #automation #generative

Automatic generation and characterization of CMOS polycells (CML, BRC, SJ), pp. 220–224.

DAC-1979-UeharaC #array #functional #layout

Optimal layout of CMOS functional arrays (TU, WMvC), pp. 287–289.

DAC-1976-Case #analysis #fault #logic

Analysis of actual fault mechanisms in CMOS logic gates (GRC), pp. 265–270.