4 papers:
DATE-2015-SunZLZZGSKRLZY #design #memory management- From device to system: cross-layer design exploration of racetrack memory (GS, CZ, HL, YZ, WZ, YG, YS, JOK, DR, YL, WZ, HY), pp. 1018–1023.
DAC-2014-MaoWZCL #architecture #memory management #using- Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory (MM, WW, YZ, YC, HHL), p. 6.
- DATE-2014-ParkYLL #graph #memory management #representation
- Accelerating graph computation with racetrack memory and pointer-assisted graph representation (EP, SY, SL, HL), pp. 1–4.
- DAC-2013-SunWL #design #memory management #power management
- Cross-layer racetrack memory design for ultra high density and low power consumption (ZS, WW, HHL), p. 6.
