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Used together with:
exploit (1)
when (1)
trajectori (1)
symbol (1)
verifi (1)

Stem transitor$ (all stems)

1 papers:

CAVCAV-1997-PandeyB #evaluation #symmetry #verification
Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation (MP, REB), pp. 244–255.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.