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Used together with:
power (7)
leakag (6)
dual (6)
size (3)
design (3)

Stem vth$ (all stems)

10 papers:

DACDAC-2012-ChajiJ #low cost
Generic low-cost characterization of Vth and mobility variations in LTPS TFTs for non-uniformity calibration of active-matrix OLED displays (GRC, JJ), pp. 182–187.
DATEDATE-2010-TieDWC #performance #reduction #scheduling
Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement (MT, HD, TW, XC), pp. 520–525.
DATEDATE-2010-YuZQB #behaviour #design #power management
Behavioral level dual-vth design for reduced leakage power with thermal awareness (JY, QZ, GQ, JB), pp. 1261–1266.
DATEDATE-2009-XuVJ #runtime
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage (HX, RV, WBJ), pp. 594–597.
DACDAC-2005-TangZB #library #optimisation #power management #synthesis
Leakage power optimization with dual-Vth library in high-level synthesis (XT, HZ, PB), pp. 202–207.
DACDAC-2004-SrivastavaSB #optimisation #power management #process #statistics #using
Statistical optimization of leakage power considering process variations using dual-Vth and sizing (AS, DS, DB), pp. 773–778.
DACDAC-2004-SrivastavaSB04a #power management #using
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment (AS, DS, DB), pp. 783–787.
DATEDATE-v1-2004-SrivastavaSB #concurrent #design #power management
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design (AS, DS, DB), pp. 718–719.
DATEDATE-2002-KimR #power management #reduction #scalability
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction (CHK, KR), pp. 163–167.
DACDAC-1999-WeiCRYD #design #power management
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications (LW, ZC, KR, YY, VD), pp. 430–435.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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