Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory
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Alexander Matveev, Nir Shavit
Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory
ASPLOS, 2015.

ASPLOS 2015
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@inproceedings{ASPLOS-2015-MatveevS,
	author        = "Alexander Matveev and Nir Shavit",
	booktitle     = "{Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems}",
	doi           = "10.1145/2694344.2694393",
	isbn          = "978-1-4503-2835-7",
	pages         = "59--71",
	publisher     = "{ACM}",
	title         = "{Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory}",
	year          = 2015,
}

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