Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo
Hierarchical top-down layout design method for VLSI chip
DAC, 1982.
@inproceedings{DAC-1982-AdachiKNS,
author = "Tohru Adachi and Hitoshi Kitazawa and Mitsuyoshi Nagatani and Tsuneta Sudo",
booktitle = "{Proceedings of the 19th Design Automation Conference}",
doi = "10.1145/800263.809291",
pages = "785--791",
publisher = "{ACM/IEEE}",
title = "{Hierarchical top-down layout design method for VLSI chip}",
year = 1982,
}