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Travelled to:
1 × USA
Collaborated with:
H.Kitazawa M.Nagatani T.Sudo
Talks about:
hierarch (1) method (1) layout (1) design (1) vlsi (1) down (1) chip (1) top (1)

Person: Tohru Adachi

DBLP DBLP: Adachi:Tohru

Contributed to:

DAC 19821982

Wrote 1 papers:

DAC-1982-AdachiKNS #design #layout #top-down
Hierarchical top-down layout design method for VLSI chip (TA, HK, MN, TS), pp. 785–791.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.