A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation
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Madhav P. Desai, Yao-Tsung Yen
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation
DAC, 1996.

DAC 1996
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@inproceedings{DAC-1996-DesaiY,
	author        = "Madhav P. Desai and Yao-Tsung Yen",
	booktitle     = "{Proceedings of the 33rd Design Automation Conference}",
	doi           = "10.1145/240518.240542",
	isbn          = "0-89791-779-0",
	pages         = "125--130",
	publisher     = "{ACM Press}",
	title         = "{A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation}",
	year          = 1996,
}

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