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Travelled to:
2 × USA
Collaborated with:
M.P.Desai J.Pan L.L.Biro J.Grodstein W.J.Grundmann
Talks about:
design (2) techniqu (1) systemat (1) circuit (1) verifi (1) custom (1) critic (1) verif (1) simul (1) devic (1)

Person: Yao-Tsung Yen

DBLP DBLP: Yen:Yao=Tsung

Contributed to:

DAC 19961996
DAC 19911991

Wrote 2 papers:

DAC-1996-DesaiY #cpu #design #simulation #using #verification
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation (MPD, YTY), pp. 125–130.
DAC-1991-PanBGGY #design #verification
Timing Verification on a 1.2M-Device Full-Custom CMOS Design (JP, LLB, JG, WJG, YTY), pp. 551–554.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.