Naran Sirisantana, Kaushik Roy
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies
DATE, 2003.
@inproceedings{DATE-2003-SirisantanaR,
acmid = "1022900",
author = "Naran Sirisantana and Kaushik Roy",
booktitle = "{Proceedings of the Eighth Conference on Design, Automation and Test in Europe}",
doi = "10.1109/DATE.2003.10131",
isbn = "0-7695-1870-2",
pages = "11160--11161",
publisher = "{IEEE Computer Society}",
title = "{Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies}",
year = 2003,
}