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Travelled to:
1 × Mexico
1 × Spain
1 × Turkey
21 × USA
6 × France
8 × Germany
Collaborated with:
S.Bhunia A.Raghunathan S.Venkataramani S.Mukhopadhyay A.Raychowdhury S.H.Choi K.Kang S.T.Chakradhar S.P.Park B.C.Paul M.Sharad K.Kim N.Banerjee V.K.Chippa S.Ghosh A.Agarwal Y.Ye Z.Chen R.Venkatesan C.Augustine S.K.Gupta D.Mohapatra A.Bansal M.M.Budnik C.H.Kim C.Koh X.Fong T.N.Vijaykumar H.Mahmoodi-Meimand K.Muhammad V.De A.A.Goud D.Fan G.Panagopoulos J.P.Kulkarni A.Ranjan H.Li D.Somasekhar G.Karakonstantis C.Lu V.Raghunathan J.Li H.Ananthan V.Balakrishnan N.Sirisantana S.Nag J.A.Abraham N.N.Mojumder D.Gizopoulos Q.Chen Y.Chen M.A.Alam L.Wei Z.Pajouhi A.Sharma C.Y.Suen P.Bhattacharya I.J.Chang P.Ndai M.Hwang T.Cakici J.Park J.H.Choi L.Chiou H.Choo J.Segura F.Dartu C.Neau M.C.Johnson K.Yogendra U.Pal R.K.Roy F.Kimura S.S.Salahuddin S.Mitra P.Sanda G.Zhong R.Zhang D.B.Janes K.Cheng S.Dey M.Rodgers A.Raha A.Sabne V.J.Kozhikkottu P.Girard N.Nicolici X.Wen A.E.Islam H.Kufluoglu A.Datta S.Yang M.D.Powell B.Falsafi M.Johnson S.G.Ramasubramanian V.S.Pai N.Bellas C.D.Antonopoulos G.Tziantzioulis V.Gupta
Talks about:
power (23) circuit (20) low (20) use (18) design (15) effici (12) comput (12) scale (11) base (11) technolog (9)

Person: Kaushik Roy

DBLP DBLP: Roy:Kaushik

Contributed to:

DAC 20152015
DATE 20152015
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20122012
DATE 20122012
DAC 20112011
DATE 20112011
DAC 20102010
DATE 20102010
ICPR 20102010
DAC 20092009
ICDAR 20092009
DAC 20082008
DATE 20082008
DAC 20072007
DATE 20072007
DAC 20062006
DATE 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DATE v1 20042004
DAC 20032003
DATE 20032003
HPCA 20032003
DAC 20022002
DATE 20022002
DAC 20012001
DATE 20012001
HPCA 20012001
DAC 20002000
DAC 19991999
DAC 19981998
DAC 19971997
DAC 19931993
DAC 19891989

Wrote 83 papers:

DAC-2015-RanjanVFRR #approximate #energy #performance
Approximate storage for energy efficient spintronic memories (AR, SV, XF, KR, AR), p. 6.
DAC-2015-VenkataramaniCR #approximate #performance
Approximate computing and the quest for computing efficiency (SV, STC, KR, AR), p. 6.
DATE-2015-GoudVRR #design #robust #symmetry
Asymmetric underlapped FinFET based robust SRAM design at 7nm node (AAG, RV, AR, KR), pp. 659–664.
DATE-2015-PajouhiFR #architecture #co-evolution #design #reliability
Device/circuit/architecture co-design of reliable STT-MRAM (ZP, XF, KR), pp. 1437–1442.
DATE-2015-RanjanRVPRR #configuration management #memory management #named #using
DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes (AR, SGR, RV, VSP, KR, AR), pp. 181–186.
DATE-2015-SharmaGR
Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems (AS, AAG, KR), pp. 1443–1448.
DATE-2015-VenkataramaniCR #approximate
Computing approximately, and efficiently (SV, STC, KR, AR), pp. 748–751.
DATE-2015-VenkatesanVFRR #energy #logic #named
Spintastic: spin-based stochastic logic for energy-efficient computing (RV, SV, XF, KR, AR), pp. 1575–1578.
DATE-2014-RanjanRVRR #approximate #named #synthesis
ASLAN: Synthesis of approximate sequential circuits (AR, AR, SV, KR, AR), pp. 1–6.
DATE-2014-RoySFY
Brain-inspired computing with spin torque devices (KR, MS, DF, KY), pp. 1–6.
DAC-2013-ChippaCRR #analysis #approximate
Analysis and characterization of inherent application resilience for approximate computing (VKC, STC, KR, AR), p. 9.
DAC-2013-SharadFR #memory management #power management
Ultra low power associative computing with spin neurons and resistive crossbar memory (MS, DF, KR), p. 6.
DATE-2013-VenkataramaniRR #approximate #configuration management #design #named #paradigm #quality
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits (SV, KR, AR), pp. 1367–1372.
DATE-2013-VenkatesanSRR #energy #named #performance #using
DWM-TAPESTRI — an energy efficient all-spin cache using domain wall shift based writes (RV, MS, KR, AR), pp. 1825–1830.
DAC-2012-ParkGMRR #architecture #design #energy #performance #using
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture (SPP, SKG, NNM, AR, KR), pp. 492–497.
DAC-2012-SharadAPR #network
Cognitive computing with spin-based neural networks (MS, CA, GP, KR), pp. 1262–1263.
DAC-2012-VenkataramaniSKRR #approximate #logic #named #synthesis
SALSA: systematic logic synthesis of approximate circuits (SV, AS, VJK, KR, AR), pp. 796–801.
DATE-2012-GuptaPMR #optimisation
Layout-aware optimization of stt mrams (SKG, SPP, NNM, KR), pp. 1455–1458.
DATE-2012-PanagopoulosAR #approach #framework #hybrid #simulation
A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach (GP, CA, KR), pp. 1443–1446.
DAC-2011-ChippaRRC #scalability #trade-off
Dynamic effort scaling: managing the quality-efficiency tradeoff (VKC, AR, KR, STC), pp. 603–608.
DAC-2011-KarakonstantisBATGR #platform
Significance driven computation on next-generation unreliable platforms (GK, NB, CDA, GT, VG, KR), pp. 290–291.
DATE-2011-LuPRR #energy #optimisation
Stage number optimization for switched capacitor power converters in micro-scale energy harvesting (CL, SPP, VR, KR), pp. 770–775.
DATE-2011-MohapatraCRR #approximate #design
Design of voltage-scalable meta-functions for approximate computing (DM, VKC, AR, KR), pp. 950–955.
DAC-2010-ChippaMRRC #algorithm #design #energy #hardware #performance #scalability
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency (VKC, DM, AR, KR, STC), pp. 555–560.
DATE-2010-LuPRR #energy #performance #transducer
Efficient power conversion for ultra low voltage micro scale energy transducers (CL, SPP, VR, KR), pp. 1602–1607.
ICPR-2010-RoySB #game studies #image #segmentation #using
Segmentation of Unideal Iris Images Using Game Theory (KR, CYS, PB), pp. 2844–2847.
DAC-2009-ChangMR #architecture #hybrid #process #video
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors (IJC, DM, KR), pp. 670–675.
DAC-2009-RoyKG #interactive
Device/circuit interactions at 22nm technology node (KR, JPK, SKG), pp. 97–102.
ICDAR-2009-PalRRK #automation #multi #recognition #string
Indian Multi-Script Full Pin-code String Recognition for Postal Automation (UP, RKR, KR, FK), pp. 456–460.
DAC-2008-KulkarniKPR #array #process
Process variation tolerant SRAM array for ultra low voltage applications (JPK, KK, SPP, KR), pp. 108–113.
DAC-2008-LiASR #array #design #memory management #modelling #probability #random #statistics
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement (JL, CA, SSS, KR), pp. 278–283.
DATE-2008-GhoshNR #adaptation #fault tolerance #novel #using
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking (SG, PN, KR), pp. 366–371.
DATE-2008-GizopoulosRGNW #power management #testing
Power-Aware Testing and Test Strategies for Low Power Devices (DG, KR, PG, NN, XW).
DATE-2008-GizopoulosRMS #case study #fault
Soft Errors: System Effects, Protection Techniques and Case Studies (DG, KR, SM, PS).
DAC-2007-KangKIAR #estimation #metric #online #reliability #using
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement (KK, KK, AEI, MAA, KR), pp. 358–363.
DAC-2007-KangKR #design #power management #using
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop (KK, KK, KR), pp. 934–939.
DAC-2007-LiKBR #flexibility #performance #power management
High Performance and Low Power Electronics on Flexible Substrate (JL, KK, AB, KR), pp. 274–275.
DATE-2007-BanerjeeKR #architecture #power management #process
Process variation tolerant low power DCT architecture (NB, GK, KR), pp. 630–635.
DATE-2007-GhoshBR #adaptation #scheduling #synthesis #using
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling (SG, SB, KR), pp. 1532–1537.
DATE-2007-HwangCR #interactive #process #scalability
Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling (MEH, TC, KR), pp. 1550–1555.
DAC-2006-AnanthanR #physics #process
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS (HA, KR), pp. 413–418.
DAC-2006-BudnikRBR
A high density, carbon nanotube capacitor for decoupling applications (MMB, AR, AB, KR), pp. 935–938.
DAC-2006-GhoshMKR #power management #reduction #self
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM (SG, SM, KK, KR), pp. 971–976.
DATE-2006-BanerjeeRMB #fine-grained #logic #power management #synthesis #using
Low power synthesis of dynamic logic circuits using fine-grained clock gating (NB, KR, HMM, SB), pp. 862–867.
DATE-2006-BudnikR #distributed #network #novel #power management #using
Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network (MMB, KR), pp. 1116–1121.
DATE-2006-ChenMBR #case study #design #power management
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design (QC, SM, AB, KR), pp. 983–988.
DATE-2006-ParkCR #adaptation #energy #image #quality #trade-off
Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off (JP, JHC, KR), pp. 520–521.
DATE-2006-PaulKKAR #design #estimation #performance #reliability
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits (BCP, KK, HK, MAA, KR), pp. 780–785.
DATE-2006-RaychowdhuryPBR #case study #comparative #power management
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies (AR, BCP, SB, KR), pp. 856–861.
DAC-2005-BhuniaBCMR #approach #novel #power management #reduction #synthesis #using
A novel synthesis approach for active leakage power reduction using dynamic supply gating (SB, NB, QC, HMM, KR), pp. 479–484.
DATE-2005-BhuniaMRR #novel #testing
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application (SB, HMM, AR, KR), pp. 1136–1141.
DATE-2005-DattaBMBR #design #modelling #pipes and filters #process #statistics
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies (AD, SB, SM, NB, KR), pp. 926–931.
DATE-2005-KangPR #analysis #statistics #using
Statistical Timing Analysis using Levelized Covariance Propagation (KK, BCP, KR), pp. 764–769.
DATE-2005-MukhopadhyayBR #analysis #logic #modelling
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits (SM, SB, KR), pp. 224–229.
DAC-2004-AgarwalKMR #design
Leakage in nano-scale technologies: mechanisms, impact and design considerations (AA, CHK, SM, KR), pp. 6–11.
DAC-2004-ChoiPR #algorithm #novel #process
Novel sizing algorithm for yield improvement under process variation in nanometer technology (SHC, BCP, KR), pp. 454–459.
DATE-v1-2004-BhuniaRR #analysis #using
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis (SB, AR, KR), pp. 704–705.
DAC-2003-MukhopadhyayRR #estimation #logic #modelling
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling (SM, AR, KR), pp. 169–174.
DAC-2003-ZhongKBR #adaptation #implementation #performance
An adaptive window-based susceptance extraction and its efficient implementation (GZ, CKK, VB, KR), pp. 728–731.
DATE-2003-AgarwalRV #architecture #pipes and filters
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology (AA, KR, TNV), pp. 10778–10783.
DATE-2003-ChiouBR #multi #power management #synthesis
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications (LYC, SB, KR), pp. 10096–10103.
DATE-2003-ChoiR #logic
A New Crosstalk Noise Model for DOMINO Logic Circuits (SHC, KR), pp. 11112–11113.
DATE-2003-ChooMR #architecture #named #power management #synthesis
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters (HC, KM, KR), pp. 10700–10705.
DATE-2003-SirisantanaR #logic #power management
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies (NS, KR), pp. 11160–11161.
HPCA-2003-LiBCVR #reduction
Deterministic Clock Gating for Microprocessor Power Reduction (HL, SB, YC, TNV, KR), pp. 113–122.
DAC-2002-AgarwalLR #named #power management
DRG-cache: a data retention gated-ground cache for low power (AA, HL, KR), pp. 473–478.
DAC-2002-BhuniaRS #analysis #detection #fault #locality #novel
A novel wavelet transform based transient current analysis for fault detection and localization (SB, KR, JS), pp. 361–366.
DAC-2002-ChoiRD #generative
Timed pattern generation for noise-on-delay calculation (SHC, KR, FD), pp. 870–873.
DATE-2002-BhuniaR #analysis #detection #fault #using
Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis (SB, KR), p. 1118.
DATE-2002-ChenBKR #reduction #using
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods (YC, VB, CKK, KR), pp. 931–935.
DATE-2002-KimR #power management #reduction #scalability
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction (CHK, KR), pp. 163–167.
DAC-2001-ZhangRKJ #3d #architecture #integration
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration (RZ, KR, CKK, DBJ), pp. 846–851.
DATE-2001-NeauMR #complexity #using
Low complexity FIR filters using factorization of perturbed coefficients (CN, KM, KR), pp. 268–272.
HPCA-2001-YangPFRV #approach #architecture
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches (SHY, MDP, BF, KR, TNV), pp. 147–157.
DAC-2000-ChuengDRR #challenge
Test challenges for deep sub-micron technologies (KTC, SD, MR, KR), pp. 142–149.
DAC-2000-SomasekharCRYD #analysis
Dynamic noise analysis in precharge-evaluate circuits (DS, SHC, KR, YY, VD), p. 243.
DAC-1999-JohnsonSR #performance #using
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS (MCJ, DS, KR), pp. 442–445.
DAC-1999-WeiCRYD #design #power management
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications (LW, ZC, KR, YY, VD), pp. 430–435.
DAC-1998-ChenR #megamodelling
A Power Macromodeling Technique Based on Power Sensitivity (ZC, KR), pp. 678–683.
DAC-1998-WeiCJRD #design #optimisation #performance
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits (LW, ZC, MJ, KR, VD), pp. 489–494.
DAC-1997-YeR #algorithm #graph #network #synthesis
A Graph-Based Synthesis Algorithm for AND/XOR Networks (YY, KR), pp. 107–112.
DAC-1993-NagR #performance
Iterative Wirability and Performance Improvement for FPGAs (SN, KR), pp. 321–325.
DAC-1989-RoyA #approach #novel #using #verification
A Novel Approach to Accurate Timing Verification Using RTL Descriptions (KR, JAA), pp. 638–641.

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