Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance
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Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance
DATE, 2005.

DATE 2005
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@inproceedings{DATE-2005-SoensPWD,
	author        = "Charlotte Soens and Geert Van der Plas and Piet Wambacq and Stéphane Donnay",
	booktitle     = "{Proceedings of the Ninth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.2005.268",
	isbn          = "0-7695-2288-2",
	pages         = "270--275",
	publisher     = "{IEEE Computer Society}",
	title         = "{Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance}",
	year          = 2005,
}

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