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circuit (150)
design (57)
model (52)
base (48)
use (46)

Stem analog$ (all stems)

358 papers:

DACDAC-2015-HuangFYZL #estimation #multi #performance
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits (QH, CF, FY, XZ, XL), p. 6.
DACDAC-2015-LahiouelZT #smt #towards #using
Towards enhancing analog circuits sizing using SMT-based techniques (OL, MHZ, ST), p. 6.
DACDAC-2015-LiuZ #configuration management #performance
A reconfigurable analog substrate for highly efficient maximum flow computation (GL, ZZ), p. 6.
DACDAC-2015-OuTC #self
Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography (HCO, KHT, YWC), p. 6.
DACDAC-2015-OuTLWC
Layout-dependent-effects-aware analytical analog placement (HCO, KHT, JYL, IPW, YWC), p. 6.
DATEDATE-2015-AfacanBPDB #hybrid #monte carlo
A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool (EA, GB, AEP, GD, IFB), pp. 1225–1228.
DATEDATE-2015-CalayirDWP #multi #programmable
Analog neuromorphic computing enabled by multi-gate programmable resistive devices (VC, MD, JAW, LP), pp. 928–931.
DATEDATE-2015-GoncalvesLCTCB #algorithm #modelling #performance #reduction
A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits (HRG, XL, MVC, VT, JMCJ, KMB), pp. 1042–1047.
DATEDATE-2015-JiaoMD #reasoning #synthesis
Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications (FJ, SM, AD), pp. 1144–1149.
DATEDATE-2015-LiaperdosAT #detection #estimation #fault #probability #testing
A method for the estimation of defect detection probability of analog/RF defect-oriented tests (JL, AA, YT), pp. 1395–1400.
DATEDATE-2015-LiaperdosSATAL #deployment #performance #using
Fast deployment of alternate analog test using Bayesian model fusion (JL, HGDS, LA, YT, AA, XL), pp. 1030–1035.
DATEDATE-2015-LourencoMH #using
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction (NCL, RM, NH), pp. 1156–1161.
DATEDATE-2015-ReichPEB #component #design #flexibility #proving
Silicon proof of the intelligent analog IP design flow for flexible automotive components (TR, HDBP, UE, RB), pp. 403–404.
DATEDATE-2015-RosenMH #architecture #implementation #multi #reliability
Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores (JvR, MM, LH), pp. 912–915.
DATEDATE-2015-ZwergerG #detection #symmetry
Detection of asymmetric aging-critical voltage conditions in analog power-down mode (MZ, HEG), pp. 1269–1272.
DACDAC-2014-LinL #analysis #parallel #reachability #verification
Parallel Hierarchical Reachability Analysis for Analog Verification (HL, PL), p. 6.
DACDAC-2014-WangOC #optimisation #performance #polynomial #synthesis
Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization (YW, MO, CC), p. 6.
DATEDATE-2014-AfacanAFDB #automation #design #modelling #optimisation
Model based hierarchical optimization strategies for analog design automation (EA, SA, FVF, GD, IFB), pp. 1–4.
DATEDATE-2014-AyariABCKR #predict
New implementions of predictive alternate analog/RF test with augmented model redundancy (HA, FA, SB, MC, VK, MR), pp. 1–4.
DATEDATE-2014-ChangOSK #approximate #estimation #statistics
Approximating the age of RF/analog circuits through re-characterization and statistical estimation (DC, SO, OS, RK), pp. 1–4.
DATEDATE-2014-HeidmannHHWPP #design #modelling
Modeling of an analog recording system design for ECoG and AP signals (NH, NH, TH, TW, DPD, SP), pp. 1–6.
DATEDATE-2014-MaliukM #framework #network #prototype
An analog non-volatile neural network platform for prototyping RF BIST solutions (DM, YM), pp. 1–6.
DATEDATE-2014-SilvaLCH #multi
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures (RMAeS, NCL, AC, NH), pp. 1–6.
DATEDATE-2014-SongDY #analysis #bound #multi #order #parametricity #performance #reduction
Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations (YS, SMPD, HY), pp. 1–6.
DATEDATE-2014-Velasco-JimenezCRF #composition #implementation #modelling #performance
Implementation issues in the hierarchical composition of performance models of analog circuits (MVJ, RCL, ER, FVF), pp. 1–6.
CHICHI-2014-YuKK
Searching for analogical ideas with crowds (LY, AK, REK), pp. 1225–1234.
CHICHI-2014-YuKK14a #distributed #generative #idea
Distributed analogical idea generation: inventing with crowds (LY, AK, REK), pp. 1245–1254.
HCIHCI-AIMT-2014-RouxelPAC #gesture #what
What You Draw Is What You Search: The Analog Gesture (BR, FP, JYA, GC), pp. 139–147.
HCIHCI-TMT-2014-BorumBF #case study #tool support
The Resilience of Analog Tools in Creative Work Practices: A Case Study of LEGO Future Lab’s Team in Billund (NB, EPB, SRFM), pp. 23–34.
ECIRECIR-2014-KumarBP #automation
Automatically Retrieving Explanatory Analogies from Webpages (VK, SB, NP), pp. 481–486.
ICPRICPR-2014-AlathariNB #segmentation #using
Femur Bone Segmentation Using a Pressure Analogy (TSA, MSN, MTB), pp. 972–977.
SACSAC-2014-RaadE #integration #ontology
Is ontology alignment like analogy?: knowledge integration with LISA (ER, JE), pp. 294–301.
DACDAC-2013-ChienOCKC
Double patterning lithography-aware analog placement (HCCC, HCO, TCC, TYK, YWC), p. 6.
DACDAC-2013-GuCL #estimation #performance #validation
Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation (CG, EC, XL), p. 7.
DACDAC-2013-HoOCT #array
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits (KHH, HCO, YWC, HFT), p. 6.
DACDAC-2013-LinLM #analysis #hybrid #kernel #reachability #verification
Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis (HL, PL, CJM), p. 6.
DACDAC-2013-LiuHLMCHZ
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine (BL, MH, HL, ZHM, YC, TH, WZ), p. 6.
DACDAC-2013-OuCC
Simultaneous analog placement and routing with current flow and current density considerations (HCO, HCCC, YWC), p. 6.
DACDAC-2013-StratigopoulosFCM #estimation #metric #multi #statistics #using
Multidimensional analog test metrics estimation using extreme value theory and statistical blockade (HGDS, PF, YC, FM), p. 7.
DACDAC-2013-TrivediCM #case study #power management
Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier (ART, SC, SM), p. 6.
DACDAC-2013-WangZSLG #modelling #performance #reuse #scalability
Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data (FW, WZ, SS, XL, CG), p. 6.
DATEDATE-2013-AhmadyanKV #algorithm #incremental #runtime #using #verification
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm (SNA, JAK, SV), pp. 21–26.
DATEDATE-2013-AhmadyanV #analysis #reachability #reduction #set
Reachability analysis of nonlinear analog circuits through iterative reachable set reduction (SNA, SV), pp. 1436–1441.
DATEDATE-2013-ChenWLL #automation #flexibility #process
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects (YLC, WRW, GRL, CNJL), pp. 1458–1461.
DATEDATE-2013-GielenM #modelling #probability #simulation
Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS (GGEG, EM), pp. 326–331.
DATEDATE-2013-HuangKCM #correlation #modelling #testing
Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests (KH, NK, JMCJ, YM), pp. 553–558.
DATEDATE-2013-JongheDDG #modelling #recursion
Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories (DdJ, DD, TD, GGEG), pp. 1448–1453.
DATEDATE-2013-MillerB #parametricity #satisfiability #verification
Formal verification of analog circuit parameters across variation utilizing SAT (MM, FB), pp. 1442–1447.
DATEDATE-2013-PanCL #agile #design #named #parallel #performance #search-based #towards
PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design (PCP, HMC, CCL), pp. 1849–1854.
DATEDATE-2013-UnutulmazDF #optimisation #using
Area optimization on fixed analog floorplans using convex area functions (AU, GD, FVF), pp. 1843–1848.
ICMLICML-c3-2013-HwangGS #categorisation #semantics #visual notation
Analogy-preserving Semantic Embedding for Visual Object Categorization (SJH, KG, FS), pp. 639–647.
DACDAC-2012-AhmadyanKV #generative
Goal-oriented stimulus generation for analog circuits (SNA, JAK, SV), pp. 1018–1023.
DACDAC-2012-JungCK #optimisation #variability
Variability-aware, discrete optimization for analog circuits (SJ, YC, JK), pp. 536–541.
DACDAC-2012-KuoHCKC #design #monte carlo #performance
Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits (CCK, WYH, YHC, JFK, YKC), pp. 1113–1118.
DACDAC-2012-OuCC #constraints #multi
Non-uniform multilevel analog routing with matching constraints (HCO, HCCC, YWC), pp. 549–554.
DACDAC-2012-SunGR #design #nondeterminism #robust
A new uncertainty budgeting based method for robust analog/mixed-signal design (JS, PG, JMWR), pp. 529–535.
DATEDATE-2012-AridhiZT #order #reduction #simulation #towards #using
Towards improving simulation of analog circuits using model order reduction (HA, MHZ, ST), pp. 1337–1342.
DATEDATE-2012-Graeb #challenge
ITRS 2011 Analog EDA Challenges and Approaches (HG), pp. 1150–1155.
DATEDATE-2012-JongheMGMTS #modelling #roadmap #testing #verification
Advances in variation-aware modeling, verification, and testing of analog ICs (DdJ, EM, GGEG, TM, BT, HGDS), pp. 1615–1620.
DATEDATE-2012-LiuMG #estimation #performance #problem
A fast analog circuit yield estimation method for medium and high dimensional problems (BL, JM, GGEG), pp. 751–756.
DATEDATE-2012-LiuTW #analysis #approach #graph #parallel #statistics
Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach (XL, SXDT, HW), pp. 852–857.
DATEDATE-2012-MaricauJG #analysis #learning #multi #reliability #using
Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection (EM, DdJ, GGEG), pp. 745–750.
DATEDATE-2012-MeissnerMLH #framework #graph #morphism #performance #synthesis #testing
Fast isomorphism testing for a graph-based analog circuit synthesis framework (MM, OM, LL, LH), pp. 757–762.
DATEDATE-2012-NarayananDZT #design #using #verification
Verifying jitter in an analog and mixed signal design using dynamic time warping (RN, AD, MHZ, ST), pp. 1413–1416.
DLTDLT-2012-KapoutsisL #automaton #finite #nondeterminism #theorem
Analogs of Fagin’s Theorem for Small Nondeterministic Finite Automata (CAK, NL), pp. 202–213.
DACDAC-2011-GongYH #analysis #monte carlo #orthogonal #performance #probability
Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials (FG, HY, LH), pp. 298–303.
DACDAC-2011-HaoTSS #analysis #bound #performance #process
Performance bound analysis of analog circuits considering process variations (ZH, SXDT, RS, GS), pp. 310–315.
DACDAC-2011-LinLCHC #random
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits (CWL, JML, YCC, CPH, SJC), pp. 528–533.
DACDAC-2011-MukherjeeFBL #automation #linear #scalability
Automatic stability checking for large linear analog integrated circuits (PM, GPF, RB, PL), pp. 304–309.
DACDAC-2011-ZhengSXHBC #array #framework #programmable
Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability (RZ, JS, CX, NH, BB, YC), pp. 322–327.
DATEDATE-2011-BoosNSHHGKS #analysis
Strategies for initial sizing and operating point analysis of analog circuits (VB, JN, MS, SH, SH, HG, DK, RS), pp. 1672–1674.
DATEDATE-2011-FerentD #automation #design #similarity
A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design features (CF, AD), pp. 1212–1217.
DATEDATE-2011-GielenMW #analysis #reliability
Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation (GGEG, EM, PHNDW), pp. 1474–1479.
DATEDATE-2011-GraupnerJW #approach #design #generative #layout #optimisation
Generator based approach for analog circuit and layout design and optimization (AG, RJ, RW), pp. 1675–1680.
DATEDATE-2011-KuppSM #correlation
Correlating inline data with final test outcomes in analog/RF devices (NK, MS, YM), pp. 812–817.
DATEDATE-2011-MiteaMHJ #automation #constraints #synthesis
Automated constraint-driven topology synthesis for analog circuits (OM, MM, LH, PJ), pp. 1662–1665.
DATEDATE-2011-NarayananZT #correctness #pattern matching #process #using
Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching (RN, MHZ, ST), pp. 1188–1191.
DATEDATE-2011-ShanbhagS #design
System-assisted analog mixed-signal design (NRS, ACS), pp. 1491–1496.
HCIHIMI-v1-2011-KomatsuO #case study #evaluation #using #visual notation
Study on Evaluation of Kawaii Colors Using Visual Analog Scale (TK, MO), pp. 103–108.
SEKESEKE-2011-Amasaki #case study #consistency #estimation #linear #nondeterminism #performance
A Study on Performance Inconsistency between Estimation by Analogy and Linear Regression (SA), pp. 485–488.
DACDAC-2010-BondD #automation #design #modelling
Automated compact dynamical modeling: an enabling tool for analog designers (BNB, LD), pp. 415–420.
DACDAC-2010-HorowitzJLLLM #analysis #equivalence #modelling
Fortifying analog models with equivalence checking and coverage analysis (MH, MJ, FL, SL, BL, JM), pp. 425–430.
DACDAC-2010-KuoCTCL #approach #behaviour
Behavior-level yield enhancement approach for large-scaled analog circuits (CCK, YLC, ICT, LYC, CNJL), pp. 903–908.
DACDAC-2010-LimKH #functional #generative #modelling #performance
An efficient test vector generation for checking analog/mixed-signal functional models (BL, JK, MAH), pp. 767–772.
DACDAC-2010-LinLHC #bound #constraints
Performance-driven analog placement considering boundary constraint (CWL, JML, CPH, SJC), pp. 292–297.
DATEDATE-2010-GomezSBF
Analog circuit test based on a digital signature (AG, RS, LB, JF), pp. 1641–1644.
DATEDATE-2010-HuangSM #fault #machine learning
Fault diagnosis of analog circuits based on machine learning (KH, HGDS, SM), pp. 1761–1766.
DATEDATE-2010-JaffariA10a #analysis #correlation #performance #variability
Correlation controlled sampling for efficient variability analysis of analog circuits (JJ, MA), pp. 1305–1308.
DATEDATE-2010-JeeraditKH #optimisation
Intent-leveraged optimization of analog circuits via homotopy (MJ, JK, MH), pp. 1614–1619.
DATEDATE-2010-LiuFG #optimisation #performance
An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique (BL, FVF, GGEG), pp. 1106–1111.
DATEDATE-2010-Mueller-GritschnederG #specification
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications (DMG, HG), pp. 1088–1093.
DATEDATE-2010-NarayananAZTP #process #verification
Formal verification of analog circuits in the presence of noise and process variation (RN, BA, MHZ, ST, LCP), pp. 1309–1312.
DACDAC-2009-LinZWC
Thermal-driven analog placement considering device matching (MPHL, HZ, MDFW, YWC), pp. 593–598.
DACDAC-2009-SunNWS #composition #contract
Contract-based system-level composition of analog circuits (XS, PN, CCW, ALSV), pp. 605–610.
DACDAC-2009-YilmazO #adaptation
Adaptive test elimination for analog/RF circuits (EY, SO), pp. 720–725.
DATEDATE-2009-BarkeGGHHPSW #formal method #verification
Formal approaches to analog circuit verification (EB, DG, HG, LH, SH, RP, SS, YW), pp. 724–729.
DATEDATE-2009-DasV #approach #automation #design #grammarware #graph grammar #multi
A graph grammar based approach to automated multi-objective analog circuit design (AD, RV), pp. 700–705.
DATEDATE-2009-GrabBCCFLS #layout #synthesis
Analog layout synthesis — Recent advances in topological approaches (HG, FB, RCL, YWC, FVF, MPHL, MS), pp. 274–279.
DATEDATE-2009-MaricauG #performance #reliability #simulation #variability
Efficient reliability simulation of analog ICs including variability and time-varying stress (EM, GGEG), pp. 1238–1241.
DATEDATE-2009-PalmersMSG #multi
Massively multi-topology sizing of analog integrated circuits (PP, TM, MS, GGEG), pp. 706–711.
DATEDATE-2009-StratigopoulosMM #set
Enrichment of limited training sets in machine-learning-based analog/RF test (HGDS, SM, YM), pp. 1668–1673.
HCIHCI-VAD-2009-SaitoMQS #development #education #mobile
Development of a Simulator of Abacus: Ancient Analog Calculator on a Mobile Phone as a Teaching Material (KS, YM, VQ, HS), pp. 204–208.
CIKMCIKM-2009-KatoOOT #query #relational #using #web
Query by analogical example: relational search using web search engine indices (MPK, HO, SO, KT), pp. 27–36.
KEODKEOD-2009-VealeL #clique #ontology
Ontological Cliques — Analogy as an Organizing Principle in Ontology Construction (TV, GL), pp. 34–41.
SIGIRSIGIR-2009-WangTFZ #community #modelling #ranking #reasoning
Ranking community answers by modeling question-answer relationships via analogical reasoning (XJW, XT, DF, LZ), pp. 179–186.
SACSAC-2009-MiyamotoTT #design #implementation #interface
Design and implementation on a pie menu interface for analog joysticks (MM, TT, MT), pp. 154–155.
DACDAC-2008-DasV #adaptation #synthesis
Topology synthesis of analog circuits based on adaptively generated building blocks (AD, RV), pp. 44–49.
DACDAC-2008-DongLY #manycore #named #parallel #simulation
WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines (WD, PL, XY), pp. 238–243.
DACDAC-2008-KimCK #parallel
Analog parallelism in ring-based VCOs (DDK, CC, JK), pp. 341–342.
DACDAC-2008-LiL #modelling #performance #statistics
Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations (XL, HL), pp. 38–43.
DACDAC-2008-LinL #clustering
Analog placement based on hierarchical module clustering (MPHL, SCL), pp. 50–55.
DATEDATE-2008-AsianVR #implementation #network
Practical Implementation of a Network Analyzer for Analog BIST Applications (MJBA, DV, AR), pp. 80–85.
DATEDATE-2008-BacinschiMKG #adaptation #bias
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs (PBB, TM, KK, MG), pp. 698–703.
DATEDATE-2008-EberleG #architecture #automation #communication #design #network #power management #scalability
A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers (WE, MG), pp. 710–715.
DATEDATE-2008-MassierGS #design
Sizing Rules for Bipolar Analog Circuit Design (TM, HEG, US), pp. 140–145.
DATEDATE-2008-MatteisDB
Advanced Analog Filters for Telecommunications (MDM, SD, AB), pp. 1316–1321.
DATEDATE-2008-PradhanV #performance #synthesis #using
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches (AP, RV), pp. 523–526.
DATEDATE-2008-SteinhorstH #model checking #specification #using
Model Checking of Analog Systems using an Analog Specification Language (SS, LH), pp. 324–329.
DATEDATE-2008-ZjajoG #analysis #fault #multi
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters (AZ, JPdG), pp. 74–79.
ICEISICEIS-ISAS2-2008-CasanovaBBF #generative
Generalization and Blending in the Generation of Entity-Relationship Schemas by Analogy (MAC, SDJB, KKB, ALF), pp. 43–48.
DACDAC-2007-LinL #novel #symmetry
Analog Placement Based on Novel Symmetry-Island Formulation (MPHL, SCL), pp. 465–470.
DACDAC-2007-LiP #correlation #multi #parametricity #performance
Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits (XL, LTP), pp. 928–933.
DACDAC-2007-McConaghyPGS #multi
Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies (TM, PP, GGEG, MS), pp. 944–947.
DACDAC-2007-WangLP #design #megamodelling
Parameterized Macromodeling for Analog System-Level Design Exploration (JW, XL, LTP), pp. 940–943.
DATEDATE-2007-Al-SammaneZT #design #verification
A symbolic methodology for the verification of analog and mixed signal designs (GAS, MHZ, ST), pp. 249–254.
DATEDATE-2007-BorremansLWR #analysis #multi #using
Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis (JB, LDL, PW, YR), pp. 261–266.
DATEDATE-2007-LataireVP #design #interactive #multi #optimisation #using
Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitations (JL, GV, RP), pp. 267–272.
DATEDATE-2007-MuellerGS #design #polynomial #programming #trade-off #using
Trade-off design of analog circuits using goal attainment and “Wave Front” sequential quadratic programming (DM, HEG, US), pp. 75–80.
DATEDATE-2007-SavojAAGH #performance
A new technique for characterization of digital-to-analog converters in high-speed systems (JS, AAA, AA, BWG, MAH), pp. 433–438.
DATEDATE-2007-ZjajoAG #interactive #monitoring #parametricity #process
Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits (AZ, MJBA, JPdG), pp. 1301–1306.
CIKMCIKM-2007-BreitmanBCF #concept #modelling
Conceptual modeling by analogy and metaphor (KKB, SDJB, MAC, ALF), pp. 865–868.
ECIRECIR-2007-MoreauCS #automation #machine learning #query #using
Automatic Morphological Query Expansion Using Analogy-Based Machine Learning (FM, VC, PS), pp. 222–233.
OOPSLAOOPSLA-2007-Grossman #garbage collection #memory management #transaction
The transactional memory / garbage collection analogy (DG), pp. 695–706.
SACSAC-2007-FanizzidE #retrieval
Instance-based retrieval by analogy (NF, Cd, FE), pp. 1398–1402.
DACDAC-2006-BorkarBCNSS #question
Tomorrow’s analog: just dead or just different? (SYB, RWB, JHC, EN, DS, CS), pp. 709–710.
DACDAC-2006-EeckelaertSGSS #design #optimisation #standard
Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard (TE, RS, GGEG, MS, WMCS), pp. 25–30.
DACDAC-2006-HammoudaSDTNBAS #design #framework #migration
Chameleon ART: a non-optimization based analog design migration framework (SH, HS, MD, MT, QN, WMB, HMA, HIS), pp. 885–888.
DACDAC-2006-WeiD #composition #development #megamodelling
Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling (YW, AD), pp. 1023–1028.
DATEDATE-2006-BuhlerKBHSSPR #design #process
DFM/DFY design for manufacturability and yield — influence of process variations in digital, analog and mixed-signal circuit design (MB, JK, JB, JH, US, RS, MP, AR), pp. 387–392.
DATEDATE-2006-FrehseKR #abstraction #refinement #using #verification
Verifying analog oscillator circuits using forward/backward abstraction refinement (GF, BHK, RAR), pp. 257–262.
DATEDATE-2006-MartensE #synthesis #top-down
Top-down heterogeneous synthesis of analog and mixed-signal systems (EM, GGEG), pp. 275–280.
DATEDATE-2006-McConaghyG #canonical #modelling #performance
Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns (TM, GGEG), pp. 269–274.
DATEDATE-2006-VandersteenBDR
Systematic stability-analysis method for analog circuits (GV, SB, PD, YR), pp. 150–155.
DATEDATE-2006-YangV #analysis #evaluation #performance #synthesis
Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis (HY, RV), pp. 283–284.
DATEDATE-2006-ZhangZD #modelling #named #parametricity #process
ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits (HZ, YZ, AD), pp. 156–161.
ICSMEICSM-2006-KuhnG
Exploiting the Analogy Between Traces and Signal Processing (AK, OG), pp. 320–329.
DACDAC-2005-BernardinisNV #design
Mixed signal design space exploration through analog platforms (FDB, PN, ALSV), pp. 875–880.
DACDAC-2005-BhattacharyaJS #optimisation
Template-driven parasitic-aware optimization of analog integrated circuit layouts (SB, NJ, CJRS), pp. 644–647.
DACDAC-2005-DingV #megamodelling #performance
A combined feasibility and performance macromodel for analog circuits (MD, RV), pp. 63–68.
DACDAC-2005-GielenME #modelling #performance #synthesis
Performance space modeling for hierarchical synthesis of analog integrated circuits (GGEG, TM, TE), pp. 881–886.
DACDAC-2005-MuellerSGS #performance
Deterministic approaches to analog performance space exploration (PSE) (DM, GS, HEG, US), pp. 869–874.
DACDAC-2005-TiwaryR #megamodelling #on-demand #scalability
Scalable trajectory methods for on-demand analog macromodel extraction (SKT, RAR), pp. 403–408.
DACDAC-2005-WeiD #behaviour #development #megamodelling
Systematic development of analog circuit structural macromodels through behavioral model decoupling (YW, AD), pp. 57–62.
DACDAC-2005-XuHLNBP #design #named #nondeterminism #optimisation #robust
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design (YX, KLH, XL, IN, SPB, LTP), pp. 632–637.
DATEDATE-2005-BadaouiV #multi #performance #synthesis
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis (RFB, RV), pp. 138–143.
DATEDATE-2005-BiswasLBP #specification
Specification Test Compaction for Analog Circuits and MEMS (SB, PL, RD(B, LTP), pp. 164–169.
DATEDATE-2005-ChienCLMRM #optimisation #pipes and filters
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters (YTC, DC, JHL, GKM, RAR, TM), pp. 279–280.
DATEDATE-2005-DingV #approach #megamodelling #modelling #performance
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling (MD, RV), pp. 1088–1089.
DATEDATE-2005-EeckelaertMG #multi #performance #synthesis #using
Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces (TE, TM, GGEG), pp. 1070–1075.
DATEDATE-2005-GielenDCDJMV #design #question
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? (GGEG, WD, PC, DD, EJ, KM, TV), pp. 36–42.
DATEDATE-2005-LiuFYO #analysis #correlation #graph #modelling
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing (FL, JJF, DVY, SO), pp. 126–131.
DATEDATE-2005-McConaghyEG #canonical #generative #named #programming #search-based
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming (TM, TE, GGEG), pp. 1082–1087.
DATEDATE-2005-SavioliCCF #approach #fault
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits (CES, CCC, JVC, ACdMF), pp. 174–175.
DATEDATE-2005-SehgalLOC #testing
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores (AS, FL, SO, KC), pp. 50–55.
DATEDATE-2005-SoensPWD #analysis #simulation
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (CS, GVdP, PW, SD), pp. 270–275.
DATEDATE-2005-SomaniCP #contest #design #optimisation #search-based
Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits (AS, PPC, AP), pp. 1064–1069.
CSLCSL-2005-Baaz #reasoning
Note on Formal Analogical Reasoning in the Juridical Context (MB), pp. 18–26.
DACDAC-2004-BhattacharyaJHS #design #scalability
Correct-by-construction layout-centric retargeting of large analog designs (SB, NJ, RH, CJRS), pp. 139–144.
DACDAC-2004-LiXLGP #approach #simulation
A frequency relaxation approach for analog/RF system-level simulation (XL, YX, PL, PG, LTP), pp. 842–847.
DACDAC-2004-RutenbarBMPPSW #question
Will Moore’s Law rule in the land of analog? (RAR, ARB, THYM, EP, RP, CS, JW), p. 633.
DACDAC-2004-TanGQ #analysis #approach #scalability
Hierarchical approach to exact symbolic analysis of large analog circuits (SXDT, WG, ZQ), pp. 860–863.
DACDAC-2004-XuPB #layout #named #optimisation
ORACLE: optimization with recourse of analog circuits including layout extraction (YX, LTP, SPB), pp. 151–154.
DATEDATE-v1-2004-BernardinisS #design
A Methodology for System-Level Analog Design Space Exploration (FDB, ALSV), pp. 676–677.
DATEDATE-v1-2004-BhuniaRR #analysis #using
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis (SB, AR, KR), pp. 704–705.
DATEDATE-v1-2004-HuangM #behaviour #identification #modelling
Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits (XH, HAM), pp. 460–467.
DATEDATE-v1-2004-KielyG #modelling #performance #using
Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines (TK, GGEG), pp. 448–453.
DATEDATE-v1-2004-LeveugleA #fault #injection
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow (RL, AA), pp. 590–595.
DATEDATE-v1-2004-MartensG #architecture #design
A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design (EM, GGEG), pp. 436–441.
DATEDATE-v1-2004-NagariN #algorithm #multi
A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs (AN, GN), pp. 76–81.
DATEDATE-v1-2004-NathkeBHB #automation #behaviour #generative
Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques (LN, VB, LH, EB), pp. 442–447.
DATEDATE-v1-2004-NegreirosCS #low cost #testing
Low Cost Analog Testing of RF Signal Paths (MN, LC, AAS), pp. 292–297.
DATEDATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.
DATEDATE-v1-2004-TanQL #modelling #scalability #simulation
Hierarchical Modeling and Simulation of Large Analog Circuits (SXDT, ZQ, HL), pp. 740–741.
DATEDATE-v1-2004-VazquezLHRH #parametricity #self
A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications (DV, GL, GH, AR, JLH), pp. 298–305.
DATEDATE-v2-2004-AgarwalSYV #estimation
Accurate Estimation of Parasitic Capacitances in Analog Circuits (AA, HS, VY, RV), pp. 1364–1365.
ITiCSEITiCSE-WGR-2004-Mason #education
Teaching by analogy: the switch statement (JM), pp. 105–107.
ICALPICALP-2004-BournezH
An Analog Characterization of Elementarily Computable Functions over the Real Numbers (OB, EH), pp. 269–280.
ICEISICEIS-v2-2004-AuerGB #estimation #visualisation
Visualizing Software Project Analogies to Support Cost Estimation (MA, BG, SB), pp. 61–68.
TOOLSTOOLS-USA-2003-HamzaE04 #analysis #problem
Applying Analysis Patterns Through Analogy: Problems and Solutions (HSH, MEF), pp. 197–208.
DACDAC-2003-BernardinisJS #performance #representation
Support vector machines for analog circuit performance representation (FDB, MIJ, ALSV), pp. 964–969.
DACDAC-2003-Hershenson #design #performance
Efficient description of the design space of analog circuits (MdMH), pp. 970–973.
DACDAC-2003-LiLXP #analysis #megamodelling
Analog and RF circuit macromodels for system-level analysis (XL, PL, YX, LTP), pp. 478–483.
DACDAC-2003-MantheLS #analysis
Symbolic analysis of analog circuits with hard nonlinearity (AM, ZL, CJRS), pp. 542–545.
DACDAC-2003-NegreirosCS #low cost
Ultimate low cost analog BIST (MN, LC, AAS), pp. 570–573.
DACDAC-2003-StehrGA #analysis #bound #performance #trade-off
Performance trade-off analysis of analog circuits by normal-boundary intersection (GS, HEG, KA), pp. 958–963.
DACDAC-2003-VasilyevRW #algorithm #generative #modelling
A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS (DV, MR, JW), pp. 490–495.
DATEDATE-2003-DoboliGD #clustering #modelling #network #using
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering (SD, GG, AD), pp. 11098–11099.
DATEDATE-2003-EberleVWDGM #automation #behaviour #modelling #simulation
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver (WE, GV, PW, SD, GGEG, HDM), pp. 10642–10649.
DATEDATE-2003-GirardiB #automation #generative #layout #named
LIT — An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks (AG, SB), pp. 11106–11107.
DATEDATE-2003-IskanderDAMHSM #synthesis #using
Synthesis of CMOS Analog Cells Using AMIGO (RI, MD, MA, MM, NH, NS, SM), pp. 20297–20302.
DATEDATE-2003-MantheLSM #analysis
Symbolic Analysis of Nonlinear Analog Circuits (AM, ZL, CJRS, KM), pp. 11108–11109.
DATEDATE-2003-SmedtG #bound #design #named
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits (BDS, GGEG), pp. 10256–10263.
DACDAC-2002-BrunoliHJKMM #question
Analog intellectual property: now? Or never? (MB, MH, FJ, RK, RM, AJM), pp. 181–182.
DACDAC-2002-DaemsGS #modelling #performance
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits (WD, GGEG, WMCS), pp. 431–436.
DACDAC-2002-HartongHB #algorithm #model checking #verification
Model checking algorithms for analog verification (WH, LH, EB), pp. 542–547.
DACDAC-2002-LiuSRC #data mining #design #megamodelling #mining #scalability
Remembrance of circuits past: macromodeling by data mining in large analog design spaces (HL, AS, RAR, LRC), pp. 437–442.
DATEDATE-2002-CarmonaJDER #design #programmable
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip (RCG, FJG, RDC, SEM, ÁRV), pp. 362–366.
DATEDATE-2002-DaemsGS #approach #linear #performance
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics (WD, GGEG, WMCS), pp. 268–273.
DATEDATE-2002-DoboliV #co-evolution #design #functional #specification
A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems (AD, RV), pp. 760–767.
DATEDATE-2002-GorenZGGLASW #approach #design
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach (DG, MZ, TCG, RG, BL, AA, AS, IAW), pp. 804–811.
DATEDATE-2002-GuardianiMDSZXL #optimisation #testing
Analog IP Testing: Diagnosis and Optimization (CG, PM, LD, SS, SZ, WX, SL), pp. 192–196.
DATEDATE-2002-HartongHB #approach #model checking
An Approach to Model Checking for Nonlinear Analog Systems (WH, LH, EB), p. 1080.
DATEDATE-2002-Hieu #analysis #design #feedback #linear #optimisation
Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis (TcH), p. 1104.
DATEDATE-2002-JerkeL #analysis #verification
Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits (GJ, JL), pp. 464–469.
DATEDATE-2002-LinLC #feedback #performance
An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits (JWL, CLL, JEC), p. 1119.
DATEDATE-2002-LuchettaMP #comparison #fault
Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques (AL, SM, MCP), p. 1105.
DATEDATE-2002-PoppOHB #analysis #automation #parametricity
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits (RP, JO, LH, EB), pp. 274–278.
DATEDATE-2002-PronathGA #design #fault #float
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits (MP, HEG, KA), pp. 78–83.
DATEDATE-2002-SchwenckerSPG #adaptation #parametricity #set #using #worst-case
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets (RS, FS, MP, HEG), pp. 581–585.
DATEDATE-2002-SommerRHGMMECSN #design #layout #specification #top-down
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications (RS, IRH, EH, UG, PM, FM, KE, CC, PS, GN), pp. 884–891.
VISSOFTVISSOFT-2002-Ploix #source code
Analogical Representations of Programs (DP), pp. 61–69.
CAVCAV-2002-HartongHB #model checking #modelling #on the
On Discrete Modeling and Model Checking for Nonlinear Analog Systems (WH, LH, EB), pp. 401–413.
SATSAT-2002-TakenakaH #algorithm #problem #satisfiability
An analog algorithm for the satisfiability problem (YT, AH), p. 40.
DACDAC-2001-GanesanV #behaviour #clustering #synthesis
Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems (SG, RV), pp. 133–138.
DACDAC-2001-VerhaegenG #analysis #linear #performance #scalability
Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits (WV, GGEG), pp. 139–144.
DATEDATE-2001-Burdiek #generative #programming #using
Generation of optimum test stimuli for nonlinear analog circuits using nonlinear — programming and time-domain sensitivities (BB), pp. 603–609.
DATEDATE-2001-CherubalC #generative #parametricity #testing
Test generation based diagnosis of device parameters for analog circuits (SC, AC), pp. 596–602.
DATEDATE-2001-DessoukyKLG #case study #design #reuse
Analog design for reuse — case study: very low-voltage sigma-delta modulator (MD, AK, MML, AG), pp. 353–360.
DATEDATE-2001-DoboliV #analysis #network #scalability
A regularity-based hierarchical symbolic analysis method for large-scale analog networks (AD, RV), p. 806.
DATEDATE-2001-Fiori
Susceptibility of analog cells to substrate interference (FF), p. 814.
DATEDATE-2001-JingnanVH #embedded #library
A Skill-based library for retargetable embedded analog cores (XJ, JCV, NH), pp. 768–769.
DATEDATE-2001-LienigJA #approach #named
AnalogRouter: a new approach of current-driven routing for analog circuits (JL, GJ, TA), p. 819.
DATEDATE-2001-MadridPAR #design #modelling #reuse
Analog/mixed-signal IP modeling for design reuse (NMM, EJP, AJA, AR), pp. 766–767.
SEKESEKE-2001-JorgensenIS #estimation #towards
Software effort estimation by analogy and regression toward the mean (MJ, UI, DIKS), pp. 268–274.
DACDAC-2000-AdlerBHB #verification
A current driven routing and verification methodology for analog applications (TA, HB, LH, EB), pp. 385–389.
DACDAC-2000-GaurdianiSMSC #bound #component #constant #simulation #statistics
An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects (CG, SS, PM, PS, DC), pp. 15–18.
DACDAC-2000-PhelpsKRCH #case study #synthesis
A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC (RP, MK, RAR, LRC, JRH), pp. 1–6.
DACDAC-2000-PiS #analysis #approach #diagrams #multi
Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits (TP, CJRS), pp. 19–22.
DACDAC-2000-SaabHK
Closing the gap between analog and digital (KS, NBH, BK), pp. 774–779.
DATEDATE-2000-AdlerB #multi
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications (TA, EB), pp. 446–450.
DATEDATE-2000-CarroSNJF #component
Non-Linear Components for Mixed Circuits Analog Front-End (LC, AAdSJ, MN, GPJ, DTF), pp. 544–549.
DATEDATE-2000-CotaRABCL #reuse
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte (ÉFC, MR, FA, YB, LC, ML), pp. 226–230.
DATEDATE-2000-DessoukyLP #performance #synthesis
Layout-Oriented Synthesis of High Performance Analog Circuits (MD, MML, JP), pp. 53–57.
DATEDATE-2000-GanesanV #array #programmable
Technology Mapping and Retargeting for Field-Programmable Analog Arrays (SG, RV), pp. 58–64.
DATEDATE-2000-GuerraRFR #analysis #approach #scalability
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits (OG, ER, FVF, ÁRV), pp. 48–52.
DATEDATE-2000-PaulusKT #constraints #optimisation
Area Optimization of Analog Circuits Considering Matching Constraints (CP, UK, RT), p. 738.
DATEDATE-2000-SchwenckerSGA #automation #bound #design
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits (RS, FS, HEG, KA), pp. 42–47.
DATEDATE-2000-WambacqDDEB #communication #modelling
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits (PW, PD, SD, ME, IB), pp. 350–354.
ICSEICSE-2000-Pisan #specification #using
Extending requirement specifications using analogy (YP), pp. 70–76.
DACDAC-1999-BalasaL #layout #representation #using
Module Placement for Analog Layout Using the Sequence-Pair Representation (FB, KL), pp. 274–279.
DACDAC-1999-DaemsGS #analysis #complexity #reduction
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits (WD, GGEG, WMCS), pp. 958–963.
DACDAC-1999-DoboliNDGV #behaviour #design #synthesis #using
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration (AD, ANA, NRD, SG, RV), pp. 951–957.
DACDAC-1999-HarjaniV #fault #parametricity
Digital Aetection of Analog Parametric Faults in SC Filters (RH, BV), pp. 772–777.
DACDAC-1999-KrasnickiPRC #named #performance #synthesis
MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells (MK, RP, RAR, LRC), pp. 945–950.
DATEDATE-1999-CherubalC #fault #functional #parametricity #using
Parametric Fault Diagnosis for Analog Systems Using Functional Mapping (SC, AC), p. 195–?.
DATEDATE-1999-CotaCL #adaptation #fault #linear #using
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester (ÉFC, LC, ML), pp. 184–188.
DATEDATE-1999-DabrowskiP #case study #experience #modelling
Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique (JD, AP), pp. 790–791.
DATEDATE-1999-DhanwadaNV #constraints #synthesis #using
Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis (NRD, ANA, RV), p. 328–?.
DATEDATE-1999-DoboliV #architecture #behaviour #compilation #generative #synthesis
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems (AD, RV), pp. 338–345.
DATEDATE-1999-GomesC #testing #using
Minimal Length Diagnostic Tests for Analog Circuits using Test History (AVG, AC), pp. 189–194.
DATEDATE-1999-NovakHK #analysis #on the
On Analog Signature Analysis (FN, BH, SK), p. 249–?.
DATEDATE-1999-Nunez-AldanaV #effectiveness #performance #synthesis
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis (ANA, RV), pp. 406–411.
DATEDATE-1999-SchwenckerEGA #automation #constraints
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints (RS, JE, HEG, KA), pp. 323–327.
DATEDATE-1999-TanS #diagrams #scalability #using
Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams (XDT, CJRS), pp. 448–453.
DATEDATE-1999-YangZ #fault #performance #robust #simulation
Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits (ZRY, MZ), pp. 244–248.
ITiCSEITiCSE-1999-Levin #education
Use of a soundcard in teaching audio frequency and analog modem communications (MHL), pp. 79–83.
SACSAC-1999-ChiangN #reuse #specification
Constructing Reusable Specifications Through Analogy (CCC, DN), pp. 586–592.
DACDAC-1998-ArsintescuCMCK #constraints
General AC Constraint Transformation for Analog ICs (BGA, EC, EM, UC, WHK), pp. 38–43.
DACDAC-1998-CarroN #adaptation #algorithm #performance
Efficient Analog Test Methodology Based on Adaptive Algorithms (LC, MN), pp. 32–37.
DATEDATE-1998-AdlerS #design #interactive
An Interactive Router for Analog IC Design (TA, JS), pp. 414–420.
DATEDATE-1998-ArsintescuO #constraints #layout
Constraints Space Management for the Layout of Analog IC’s (BGA, RHJMO), pp. 971–972.
DATEDATE-1998-DroegeTH #named
EASY — a System for Computer-Aided Examination of Analog Circuits (GD, MT, EHH), pp. 644–648.
DATEDATE-1998-EckmuellerGG
Hierarchical Characterization of Analog Integrated CMOS Circuits (JE, MG, HEG), pp. 636–643.
DATEDATE-1998-HedrichB #approach #formal method #linear #parametricity #verification
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances (LH, EB), pp. 649–654.
DATEDATE-1998-LindermeirVG #design #detection #fault #metric #parametricity
Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults (WML, TJV, HEG), pp. 822–827.
DATEDATE-1998-PrietoRGPHR #approach #design #fault #layout #predict #testing
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits (JAP, AR, IAG, EJP, JLH, AMDR), pp. 905–909.
DATEDATE-1998-RenovellAB #implementation #multi
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits (MR, FA, YB), pp. 815–821.
DATEDATE-1998-RosenbergerH #approach #behaviour #functional #modelling #simulation
A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks (RR, SAH), pp. 721–728.
DATEDATE-1998-TianS #fault #performance #simulation
Efficient DC Fault Simulation of Nonlinear Analog Circuits (MWT, CJRS), pp. 899–904.
DATEDATE-1998-VandenbusscheDLGS #design #interface #specification #top-down
Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon (JV, SD, FL, GGEG, WMCS), pp. 716–720.
DATEDATE-1998-Velasco-MedinaCN #detection #fault #injection #linear #using
Fault Detection for Linear Analog Circuits Using Current Injection (JVM, TC, MN), pp. 987–988.
DATEDATE-1998-WolfK #automation #generative #optimisation
Automatic Topology Optimization for Analog Module Generators (MW, UK), pp. 961–962.
DACDAC-1997-TianS #agile #fault #parametricity #simulation
Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances (MWT, CJRS), pp. 275–280.
DATEEDTC-1997-ArabiK #performance #testing #using
Efficient and accurate testing of analog-to-digital converters using oscillation-test method (KA, BK), pp. 348–352.
DATEEDTC-1997-DonnayGSKLB #interface #synthesis
High-level synthesis of analog sensor interface front-ends (SD, GGEG, WMCS, WK, DL, WvB), pp. 56–60.
DATEEDTC-1997-Garcia-VargasGFR #algorithm #analysis #generative #scalability
An algorithm for numerical reference generation in symbolic analysis of large analog circuits (IGV, MG, FVF, ÁRV), pp. 395–399.
DATEEDTC-1997-KaalK #generative #metaprogramming #testing
Compact structural test generation for analog macros (VK, HGK), pp. 581–587.
DATEEDTC-1997-PrietoRQH #algorithm #optimisation
A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs (JAP, AR, JMQ, JLH), pp. 389–394.
DATEEDTC-1997-RenovellAB
On-chip analog output response compaction (MR, FA, YB), pp. 568–572.
DATEEDTC-1997-RomanowiczLLRABMP #hardware #modelling #simulation #transducer #using
Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language (BR, ML, PL, PR, HPA, AB, VM, FP), pp. 119–123.
DATEEDTC-1997-SzekelyPPRC #simulation
SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells (VS, AP, AP, MR, AC), p. 617.
DATEEDTC-1997-WolfK #generative #independence
Application independent module generation in analog layouts (MW, UK), p. 624.
RERE-1997-MassonetL #framework #requirements #reuse
Analogical Reuse of Requirements Frameworks (PM, AvL), p. 26–?.
CADECADE-1997-DefourneauxP #proving
Partial Matching for Analogy Discovery in Proofs and Counter-Examples (GD, NP), pp. 431–445.
DACDAC-1996-BorchersHB #behaviour #equation #generative
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits (CB, LH, EB), pp. 236–239.
DACDAC-1996-MiyaharaOM #design
Design Methodology for Analog High Frequency ICs (YM, YO, SM), pp. 503–508.
ICMLICML-1996-Roverso #abstraction #knowledge base #multi #scalability
Analogy Access by Mapping Spreading and Abstraction in Large, Multifunctional Knowledge Bases (DR), pp. 418–426.
ICSEICSE-1996-ShepperdSK #estimation #using
Effort Estimation Using Analogy (MJS, CS, BK), pp. 170–178.
CADECADE-1996-MelisW #proving #theorem proving
Internal Analogy in Theorem Proving (EM, JW), pp. 92–105.
DACDAC-1995-LampaertGS
Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits (KL, GGEG, WMCS), pp. 445–449.
DACDAC-1995-VinnakotaHS #design #difference
System-Level Design for Test of Fully Differential Analog Circuits (BV, RH, NJS), pp. 450–454.
DACDAC-1994-CharbonMPS #optimisation
Simultaneous Placement and Module Optimization of Analog IC’s (EC, EM, DP, ALSV), pp. 31–35.
DACDAC-1994-OchottaRC #agile #named #synthesis #tool support
ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits (ESO, RAR, LRC), pp. 24–30.
DATEEDAC-1994-AhmedCC #approach #fault #modelling #optimisation #using
A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation (SA, PYKC, PC), p. 665.
DATEEDAC-1994-DongenR #array #design
Advanced Analog Circuit Design on a Digital Sea-of-Gates Array (RvD, VR), pp. 70–74.
DATEEDAC-1994-DonnaySGSKL #automation #design
A Methodology for Analog Design Automation in Mixed-Signal ASICs (SD, KS, GGEG, WMCS, WK, DL), pp. 530–534.
DATEEDAC-1994-GevaertVNS
Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front End (DG, JV, JN, JS), pp. 75–79.
DATEEDAC-1994-VermeirenSE #fault #simulation
A Suggestion for Accelerating the Analog Fault Simulation (WV, BS, GE), p. 662.
CHICHI-1994-RiemanLYP94a #architecture #consistency #interface #reasoning #why
Why is a raven like a writing desk?: lessons in interface consistency and analogical reasoning from two cognitive architectures (JR, CHL, RMY, PGP), pp. 438–444.
SEKESEKE-1994-Alexander #generative #specification
Combining transformational and derivational analogy in Larch specification generation (PA), pp. 131–138.
DACDAC-1993-LiuCS #behaviour #simulation #using #verification
Analog System Verification in the Presence of Parasitics Using Behavioral Simulation (EWYL, HCC, ALSV), pp. 159–163.
DACDAC-1993-MogakiSKH #approach #layout
Cooperative Approach to a Practical Analog LSI Layout System (MM, YS, MK, TH), pp. 544–549.
DACDAC-1993-Nagaraj #optimisation #performance
A New Optimizer for Performance Optimization of Analog Integrated Circuits (NSN), pp. 148–153.
DACDAC-1993-NagiCA #fault #named
DRAFTS: Discretized Analog Circuit Fault Simulator (NN, AC, JAA), pp. 509–514.
ASEKBSE-1993-LeeH #design #retrieval #reuse
An Analogy-Based Retrieval Mechanism for Software Design Reuse (HYL, MTH), p. 22.
SIGMODSIGMOD-1993-RakowM #video
The V3 Video Server — Managing Analog and Digital Video Clips (TCR, PM), pp. 556–557.
STOCSTOC-1993-Maass #bound #complexity #learning
Bounds for the computational power and learning complexity of analog neural nets (WM), pp. 335–344.
HCIHCI-SHI-1993-Boase-JelinekM #reasoning
Role of Analogical Reasoning as a Tool for Training (DMBJ, DM), pp. 760–765.
CAiSECAiSE-1993-SpanoudakisC #approach #concept #modelling #reuse #similarity
Similarity for Analogical Software Reuse: A Conceptual Modelling Approach (GS, PC), pp. 483–503.
CIKMCIKM-1993-HaasAO #biology #database #information management #reasoning
Analogical Reasoning for Knowledge Discovery in a Molecular Biology Database (JH, JSA, GCO), pp. 554–564.
ICMLICML-1993-VanLehnJ #problem
Better Learners Use Analogical Problem Solving Sparingly (KV, RMJ), pp. 338–345.
SACSAC-1993-Harandi #reuse
The Role of Analogy in Software Reuse (MTH), pp. 40–47.
SACSAC-1993-LungU #analysis #approach #integration #reuse
Integration of Domain Analysis and Analogical Approach for Software Reuse (CHL, JEU), pp. 48–53.
DACDAC-1992-DharchoudhuryK #approach #design #optimisation #worst-case
An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits (AD, SMK), pp. 704–709.
DACDAC-1992-MaulikCR #approach #programming #synthesis
A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis (PCM, LRC, RAR), pp. 698–703.
ASEKBSE-1992-MatwinB #database #query #reuse
Reusing Database Queries in Analogical Domains (SM, HOB), p. 16.
KRKR-1992-MyersK #reasoning
Reasoning with Analogical Representations (KLM, KK), pp. 189–200.
ICMLML-1992-ConklinG
Spatial Analogy and Subsumption (DC, JIG), pp. 111–116.
DACDAC-1991-DonzelleDHPS #approach #automation #constraints #design
A Constraint Based Approach to Automatic Design of Analog Cells (LOD, PFD, BH, JP, PS), pp. 506–509.
DACDAC-1991-Gad-El-KarimG #generative #layout #performance
Generation of Performance Sensitivities for Analog Cell Layout (GGEK, RSG), pp. 500–505.
DACDAC-1991-HussG #testing
Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time (SDH, RSG), pp. 494–499.
DACDAC-1991-MogakiKSY #constraints #layout
A Layout Improvement Method Based on Constraint Propagation for Analog LSI’s (MM, NK, NS, YY), pp. 510–513.
ASEKBSE-1991-MaidenS #reuse #specification
Analogical Matching for Specification Reuse (NAMM, AGS), pp. 108–116.
ASEKBSE-1991-MiriryalaH #specification
The Role of Analogy in Specification Derivation (KM, MTH), pp. 117–126.
CHICHI-1991-MacLeanBYM #design
Reaching through analogy: a Design Rationale perspective on roles of analogy (AM, VB, RMY, TPM), pp. 167–172.
KRKR-1991-DierbachC #reasoning
A Formal Basis for Analogical Reasoning (CD, DLC), pp. 139–150.
ICMLML-1991-VanLehnJ #correctness #learning #physics
Learning Physics Via Explanation-Based Learning of Correctness and Analogical Search Control (KV, RMJ), pp. 110–114.
ICLPISLP-1991-Benthem #logic #programming #reasoning
Reasoning and Programming: Analogies between Logic and Computation (JvB), pp. 717–718.
DACDAC-1990-ChoudhuryS #constraints #generative
Constraint Generation for Routing Analog Circuits (UC, ALSV), pp. 561–566.
ICGTGG-1990-HessM #approach
The Four Musicians: Analogies and Expert Systems — A Graphic Approach (LH, BHM), pp. 430–445.
ICMLML-1990-Kodratoff #abduction #problem #proving #using
Using Abductive Recovery of Failed Proofs for Problem Solving by Analogy (YK), pp. 295–303.
POPLPOPL-1990-AspertiFG #proving
Implicative Formulae in the “Proofs as Computations” Analogy (AA, GLF, RG), pp. 59–71.
DACDAC-1989-RumseyS #simulation
An ASIC Methodology for Mixed Analog-Digital Simulation (MR, JS), pp. 618–621.
KRKR-1989-Leishman #concept #graph
Analogy as a Constrained Partial Correspondence Over Conceptual Graphs (DL), pp. 223–234.
KRKR-1989-Prescott #reasoning
Analogical Reasoning, Defeasible Reasoning, and the Reference Class (RP), pp. 256–265.
ICMLML-1989-RaedtB #induction
Constructive Induction by Analogy (LDR, MB), pp. 476–477.
DACDAC-1988-BerkcandL #compilation
Analog Compilation Based on Successive Decompositions (EB, MAd, WL), pp. 369–375.
DACDAC-1988-VisweswariahCC #development #verification
Model Development and Verification for High Level Analog Blocks (CV, RC, CFC), pp. 376–382.
CADECADE-1988-BrockCP #proving #reasoning
Analogical Reasoning and Proof Discovery (BB, SC, WP), pp. 454–468.
DACDAC-1987-HarjaniRC #framework #knowledge-based #prototype #synthesis
A Prototype Framework for Knowledge-Based Analog Circuit Synthesis (RH, RAR, LRC), pp. 42–49.
VLDBVLDB-1986-Yokomori #database #logic #on the #query
On Analogical Query Processing in Logic Database (TY), pp. 376–383.
DACDAC-1983-Barke #layout #verification
A layout verification system for analog bipolar integrated circuits (EB), pp. 353–359.
SIGIRSIGIR-1982-Drewes #retrieval
Retrieval of Abstracts by Analogy (BD), pp. 238–250.
DACDAC-1981-Glasser #behaviour
The analog behavior of digital integrated circuits (LAG), pp. 603–612.
DACDAC-1981-Masurkar #algorithm #development #fault #identification #network
An algorithmic pretest development for fault identification in analog networks (VM), pp. 204–212.
DACDAC-1979-SaharaKN #interactive #layout
An interactive layout system of analog printed wiring boards (KiS, KiK, IN), pp. 506–512.
DACDAC-1977-JaffeY #automation #diagrams #using
Automating analog circuit diagrams using a list processing language (RCJ, JPY), pp. 391–395.
LISPLISP-1963-Verhovsky
FNS analogous & similar (SAV), p. 16.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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