BibSLEIGH — Piet

Travelled to:

3 × USA
4 × France
4 × Germany

Collaborated with:

S.Donnay G.Vandersteen H.D.Man P.Dobrovolný M.Engels I.Bolsens G.G.E.Gielen G.V.d.Plas Y.Rolain M.Badaroglu W.Eberle J.Borremans L.D.Locht C.Soens M.Goffioul F.Verbeyst H.Ziad K.Tiri I.Verbauwhede J.Schoukens J.R.Phillips J.S.Roychowdhury B.Yang D.E.Long A.Demir

Talks about:

nonlinear (6) circuit (6) analysi (5) substrat (4) analog (4) simul (4) model (4) digit (4) high (4) transceiv (3)

Person: Piet Wambacq

DBLP: Wambacq:Piet

Contributed to:

2007

2005

2004

2003

2002

2001

2000

1999

Wrote 14 papers:

DATE-2007-BorremansLWR #analysis #multi #using: Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis (JB, LDL, PW, YR), pp. 261–266.
DATE-2005-SoensPWD #analysis #simulation: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (CS, GVdP, PW, SD), pp. 270–275.
DAC-2004-PlasBVDWDGM #simulation: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (GVdP, MB, GV, PD, PW, SD, GGEG, HDM), pp. 854–859.
DATE-v1-2004-BadarogluWPDGM #reduction: Digital Ground Bounce Reduction by Phase Modulation of the Clock (MB, PW, GVdP, SD, GGEG, HDM), pp. 88–93.
DATE-2003-DobrovolnyVWD #analysis #modelling: Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits (PD, GV, PW, SD), pp. 10624–10629.
DATE-2003-EberleVWDGM #automation #behaviour #modelling #simulation: Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver (WE, GV, PW, SD, GGEG, HDM), pp. 10642–10649.
DAC-2002-BadarogluTDWMVG #optimisation #reduction #using: Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.
DATE-2002-GoffioulWVD #analysis #approach #architecture #using: Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach (MG, PW, GV, SD), pp. 352–356.
DATE-2002-VandersteenWDV #evaluation #performance: High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions (GV, PW, SD, FV), pp. 586–590.
DATE-2001-VandersteenWRSDEB #estimation #multi #performance: Efficient bit-error-rate estimation of multicarrier transceivers (GV, PW, YR, JS, SD, ME, IB), pp. 164–168.
DATE-2001-WambacqVPREYLD: CAD for RF circuits (PW, GV, JRP, JSR, WE, BY, DEL, AD), pp. 520–529.
DAC-2000-VandersteenWRDDEB #data flow #performance #simulation: A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers (GV, PW, YR, PD, SD, ME, IB), pp. 440–445.
DATE-2000-WambacqDDEB #communication #modelling: Compact Modeling of Nonlinear Distortion in Analog Communication Circuits (PW, PD, SD, ME, IB), pp. 350–354.
DATE-1999-WambacqDZEMB: A Single-Package Solution for Wireless Transceivers (PW, SD, HZ, ME, HDM, IB), p. 425–?.