Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models
DATE, 2011.
@inproceedings{DATE-2011-KimCSY,
author = "Dusung Kim and Maciej J. Ciesielski and Kyuho Shim and Seiyang Yang",
booktitle = "{Proceedings of the 15th Conference on Design, Automation and Test in Europe}",
isbn = "978-1-61284-208-0",
pages = "1584--1589",
publisher = "{IEEE}",
title = "{Temporal parallel simulation: A fast gate-level HDL simulation using higher level models}",
year = 2011,
}