18 papers:
DAC-2014-AtacCLWSZWH #design #multi #standard- An HDL-Based System Design Methodology for Multistandard RF SoC’s (AA, ZC, LL, YW, MS, YZ, RW, SH), p. 6.
DATE-2014-YangHKKCPK #parallel #predict #simulation- Predictive parallel event-driven HDL simulation with a new powerful prediction strategy (SY, JH, DK, NK, DC, JP, JK), pp. 1–3.
- DATE-2011-KimCSY #modelling #parallel #performance #simulation #using
- Temporal parallel simulation: A fast gate-level HDL simulation using higher level models (DK, MJC, KS, SY), pp. 1584–1589.
- DATE-2011-KimCY #distributed #predict #simulation
- A new distributed event-driven gate-level HDL simulation by accurate prediction (DK, MJC, SY), pp. 547–550.
ASE-2010-DuleySK #algorithm #difference- A program differencing algorithm for verilog HDL (AD, CS, MK), pp. 477–486.
- DATE-2006-Al-JunaidK #modelling #using
- HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope (HAJ, TJK), pp. 644–645.
- DAC-2003-SaifhashemiP #abstraction #framework #modelling
- Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction (AS, HP), pp. 330–333.
- DAC-1999-FallahAD #generative #simulation
- Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage (FF, PA, SD), pp. 666–671.
- DATE-1999-SantosT #fault #simulation #using
- Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL (MBS, JPT), p. 549–?.
- DAC-1998-FallahDK #functional #generative #linear #modelling #programming #satisfiability #using
- Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability (FF, SD, KK), pp. 528–533.
- EDTC-1997-HofmannGSMMSKC #generative
- Generation of the HDL-A-model of a micromembrane from its finite-element-description (KH, MG, NS, AM, SM, JS, JMK, BC), pp. 108–112.
- EDTC-1997-LeupersM #generative #modelling
- Retargetable generation of code selectors from HDL processor models (RL, PM), pp. 140–144.
- DAC-1996-LiG #optimisation #using
- HDL Optimization Using Timed Decision Tables (JL, RKG), pp. 51–54.
- DAC-1995-KnappLMM #behaviour #specification #synthesis #validation
- Behavioral Synthesis Methodology for HDL-Based Specification and Validation (DK, TL, DM, RM), pp. 286–291.
LICS-1995-Gordon #challenge #semantics- The Semantic Challenge of Verilog HDL (MJCG), pp. 136–145.
RTA-1995-Boulton #higher-order #semantics #strict- A Restricted Form on Higher-Order Rewriting Applied to an HDL Semantics (RJB), pp. 309–323.
- DAC-1982-Rawlings
- VHSIC HDL (JBR), p. 213.
- DAC-1980-Shiva #logic #synthesis
- Combinational logic synthesis from an HDL description (SGS), pp. 550–555.
