Proceedings of the Seventh International Symposium on High-Performance Computer Architecture
HPCA, 2001.

@proceedings{HPCA-2001,
	address       = "Nuevo Leone, Mexico",
	ee            = "http://www.computer.org/csdl/proceedings/hpca/2001/1019/00/index.html",
	isbn          = "0-7695-1019-1",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Seventh International Symposium on High-Performance Computer Architecture}",
	year          = 2001,
}

Contents (26 items)

7 ×#architecture
4 ×#memory management
3 ×#hardware
3 ×#multi
3 ×#predict
3 ×#scalability
2 ×#branch
2 ×#energy
2 ×#named
2 ×#performance

HPCA-2001-LeeSNT #architecture #stack

Stack Value File: Custom Microarchitecture for the Stack (HHSL, MS, CJN, GST), pp. 5–14.

HPCA-2001-WangWKRS #execution #scheduling

Register Renaming and Scheduling for Dynamic Execution of Predicated Code (PHW, HW, RMK, KR, JPS), pp. 15–25.

HPCA-2001-MichaudS #data flow #scalability

Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors (PM, AS), pp. 27–36.

HPCA-2001-RothS #data-driven #multi #thread

Speculative Data-Driven Multithreading (AR, GSS), pp. 37–48.

HPCA-2001-QiuD #memory management #towards

Towards Virtually-Addressed Memory Hierarchies (XQ, MD), pp. 51–62.

HPCA-2001-FangZCHM #hardware #online

Reevaluating Online Superpage Promotion with Hardware Support (ZF, LZ, JBC, WCH, SAM), pp. 63–72.

HPCA-2001-AbaliFSPS #hardware #in memory #memory management #performance

Performance of Hardware Compressed Main Memory (BA, HF, XS, DEP, TBS), pp. 73–81.

HPCA-2001-MoshovosMFC #energy #named

JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers (AM, GM, BF, ANC), pp. 85–96.

HPCA-2001-AcacioGGD #architecture #multi #scalability

A New Scalable Directory Architecture for Large-Scale Multiprocessors (MEA, JG, JMG, JD), pp. 97–106.

HPCA-2001-ThottethodiRM #multi #network #self

Self-Tuned Congestion Control for Multiprocessor Networks (MT, ARL, SSM), pp. 107–118.

HPCA-2001-LeeST #architecture #automation #memory management

Automatically Mapping Code on an Intelligent Memory Architecture (JL, YS, JT), pp. 121–132.

HPCA-2001-KailasEA #clustering #code generation #framework #named

CARS: A New Code Generation Framework for Clustered ILP Processors (KK, KE, AKA), pp. 133–143.

HPCA-2001-YangPFRV #approach #architecture

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches (SHY, MDP, BF, KR, TNV), pp. 147–157.

HPCA-2001-DelaluzKVSI #energy #hardware #using

DRAM Energy Management Using Software and Hardware Directed Power Mode Control (VD, MTK, NV, AS, MJI), pp. 159–169.

HPCA-2001-BrooksM

Dynamic Thermal Management for High-Performance Microprocessors (DMB, MM), pp. 171–182.

HPCA-2001-TuneLTC #predict

Dynamic Prediction of Critical Path Instructions (ET, DL, DMT, BC), pp. 185–195.

HPCA-2001-JimenezL #branch #predict

Dynamic Branch Prediction with Perceptrons (DAJ, CL), pp. 197–206.

HPCA-2001-GoemanVB #difference #performance #predict

Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency (BG, HV, KDB), pp. 207–216.

HPCA-2001-CorbalEV #generative

DLP + TLP Processors for the Next Generation of Media Workloads (JC, RE, MV), pp. 219–228.

HPCA-2001-CainRML #architecture #evaluation #java

An Architectural Evaluation of Java TPC-W (HWC, RR, MM, MHL), pp. 229–240.

HPCA-2001-ZillesS #profiling #programmable

A Programmable Co-Processor for Profiling (CBZ, GSS), pp. 241–252.

HPCA-2001-PehD #architecture #pipes and filters

A Delay Model and Speculative Architecture for Pipelined Routers (LSP, WJD), pp. 255–266.

HPCA-2001-HeathKPN #architecture #communication #scalability

Quantifying the Impact of Architectural Scaling on Communication (TH, SK, RPM, TDN), pp. 267–277.

HPCA-2001-AnnavaramPD #database #graph

Call Graph Prefetching for Database Applications (MA, JMP, ESD), pp. 281–290.

HPCA-2001-SrinivasanDTCP #branch

Branch History Guided Instruction Prefetching (VS, ESD, GST, MJC, TRP), pp. 291–300.

HPCA-2001-LinRB #design #memory management

Reducing DRAM Latencies with an Integrated Memory Hierarchy Design (WFL, SKR, DB), pp. 301–312.