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Travelled to:
3 × USA
Collaborated with:
K.Keutzer S.Devadas P.Vanbekbergen S.Malik A.Saldanha R.K.Brayton A.L.Sangiovanni-Vincentelli S.Y.Liao S.W.K.Tjiang
Talks about:
circuit (2) logic (2) microprocessor (1) asynchron (1) techniqu (1) transit (1) simplif (1) certifi (1) system (1) filter (1)

Person: Albert R. Wang

DBLP DBLP: Wang:Albert_R=

Contributed to:

DAC 19951995
DAC 19921992
DAC 19891989

Wrote 4 papers:

DAC-1995-LiaoDKTW #embedded #optimisation
Code Optimization Techniques for Embedded DSP Microprocessors (SYL, SD, KK, SWKT, ARW), pp. 599–604.
DAC-1995-VanbekbergenWK #design #validation
A Design and Validation System for Asynchronous Circuits (PV, ARW, KK), pp. 725–730.
DAC-1992-DevadasKMW #logic #verification
Certified Timing Verification and the Transition Delay of a Logic Circuit (SD, KK, SM, ARW), pp. 549–555.
DAC-1989-SaldanhaWBS #logic #multi #using
Multi-level Logic Simplification Using Don’t Cares and Filters (AS, ARW, RKB, ALSV), pp. 277–282.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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